2021 22nd International Symposium on Quality Electronic Design (ISQED)最新文献_第4页

SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion SeNonDiv:使用混合存储器和关键数据转移保护非易失性存储器

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424292

Arijit Nath, Manik B. Bhosle, H. Kapoor

引用次数: 0

An End-to-end Multi-task Object Detection using Embedded GPU in Autonomous Driving 基于嵌入式GPU的自动驾驶端到端多任务目标检测

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424308

Shangli Zhou, Mimi Xie, Yufang Jin, Fei Miao, Caiwen Ding

{"title":"An End-to-end Multi-task Object Detection using Embedded GPU in Autonomous Driving","authors":"Shangli Zhou, Mimi Xie, Yufang Jin, Fei Miao, Caiwen Ding","doi":"10.1109/ISQED51717.2021.9424308","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424308","url":null,"abstract":"Autonomous driving has gained popularity due to its high reliability compared to human drivers. Autonomous vehicles combine variety of sensors to perceive their surroundings, and use deep learning (DL) to extract complicated information from the sensing data. However, there are several challenges: Many DL models have explosive model sizes, and therefore not only time consuming but also power consuming when implementing on embedded systems on vehicles, further degrading the battery life-cycle. The current on-board AI treats lane detection and car location separately. In this paper, we propose an end-to-end multi-task environment detection framework. We fuse the 3D point cloud object detection model and lane detection model, with model compression technique applied. As on-board sensors forward information to the multi-task network, it not only parallel two detection tasks to extract combination information, but also reduces entire running time of the DL model. Experiments show by adding the model compression technique, the running speed of multi-task model improves more than $2times$. Also, running time of lane detection model on Nvidia Jetson TX2 is almost $6times$ less comparing with running on CPU, which shows reasonableness of using embedded AI computing device on autonomous vehicle.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122997968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Towards Internet-of-Things for Wearable Neurotechnology 面向可穿戴神经技术的物联网

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424364

Salma Elmalaki, B. U. Demirel, Mojtaba Taherisadr, Sara Stern-Nezer, Jack J. Lin, M. A. Faruque

{"title":"Towards Internet-of-Things for Wearable Neurotechnology","authors":"Salma Elmalaki, B. U. Demirel, Mojtaba Taherisadr, Sara Stern-Nezer, Jack J. Lin, M. A. Faruque","doi":"10.1109/ISQED51717.2021.9424364","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424364","url":null,"abstract":"This paper outlines the prevalent challenges for the emerging wearable neurotechnology in modern IoT systems. We underline the recent insights in neuroscience and the ability to decode the brain circuitry with high confidence. We address the imminent challenges of translating the advanced high-cost medical setup for neural activity recording to a commodity IoT system. Emphasis is placed on non-invasive wearable sensing technology and the advances in data analytic for neurosignals. In particular, we focus on human-in-the-loop IoT systems where privacy concerns of leaking private human state and energy limitations for local data processing lay significant constraints on such systems’ architecture. Along the way, we envision applications that will reach their full potential and provide the promised functionality by embedding wearable neurotechnology in their design. We end the paper by highlighting the prominent research opportunities and challenges for designing and developing the next generation of low-cost, energy-efficient, privacy-aware, and ubiquitous wearable neurotechnology. Most of these research challenges need to be addressed from a multi-disciplinary approach. Researchers from various communities need to coordinate and collaborate to successfully advance the research, development, and standardization of such neurotechnologies for the larger benefit of society.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"1998 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Diverse Knowledge Distillation (DKD): A Solution for Improving The Robustness of Ensemble Models Against Adversarial Attacks 多元知识蒸馏(DKD):一种提高集成模型抗对抗性攻击鲁棒性的解决方案

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424353

Ali Mirzaeian, J. Kosecka, H. Homayoun, T. Mohsenin, Avesta Sasan

引用次数: 5

ACLA: An Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction ACLA:一种具有智能进位判断和修正的近似进位前瞻加法器

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424329

Shobhit Belwal, Rajat Bhattacharjya, Kaustav Goswami, D. Banerjee

引用次数: 3

On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis 高级综合中资源最小化与互联复杂性的关系

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424266

S. Dutt, Xiuyan Zhang, Ouwen Shi

{"title":"On the Correlation between Resource Minimization and Interconnect Complexities in High-Level Synthesis","authors":"S. Dutt, Xiuyan Zhang, Ouwen Shi","doi":"10.1109/ISQED51717.2021.9424266","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424266","url":null,"abstract":"As the technology node of VLSI designs advances to sub10 nm, two interconnect-centric metrics of a circuit, the interconnect complexity (either number of interconnects or wirelength/WL) and congestion, become critically important across all design stages alongside conventional resource or function-unit (FU)-centric metrics like area/number-of-FUs and leakage power. High Level synthesis (HLS), one of the earliest and most impactful design stages, rarely monitors interconnect metrics, which makes their recovery at later stages very difficult. HLS algorithms and tools typically perform FU-centric minimization via operation scheduling, module selection (S&MS) and binding. As a consequence, it mostly overlooks interconnect-based metrics. In this paper, we explore whether this can adversely affect interconnect metrics, and in general explore the correlation between FU-centric optimization in S&MS, and the resulting interconnect metrics co-optimized (along with FU metrics) in the later binding stage(s). For this purpose we develop a probabilistic analysis for post-scheduling binding to estimate interconnect metrics, and verify its accuracy by comparison to empirical results across different scheduling techniques that generate different degrees of FU optimization. Based on both empirical and analytical results we predict how interconnects metrics will pan out with different degrees of FU optimization. Finally, based on our analysis, we also provide suggestions to improve interconnect metrics for whatever FU optimization degree an available S&MS technique can achieve.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115783166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware Trojan Detection Method for Inspecting Integrated Circuits Based on Machine Learning 基于机器学习的集成电路硬件木马检测方法

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424314

Yuze Wang, Peng Liu, Xiaoxia Han, Yingtao Jiang

{"title":"Hardware Trojan Detection Method for Inspecting Integrated Circuits Based on Machine Learning","authors":"Yuze Wang, Peng Liu, Xiaoxia Han, Yingtao Jiang","doi":"10.1109/ISQED51717.2021.9424314","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424314","url":null,"abstract":"Nowadays malicious vendors can easily insert hardware Trojans into integrated circuit chips as the entire integrated chip supply chain involves numerous design houses and manufacturers on a global scale. It is thereby becoming a necessity to expose any possible hardware Trojans, if they ever exist in a chip. A typical Trojan circuit is made of a trigger and a payload that are interconnected with a trigger net. As trigger net can be viewed as the signature of a hardware Trojan, in this paper, we propose a gate-level hardware Trojan detection method and model that can be applied to screen the entire chip for trigger nets. In specific, we extract the trigger-net features for each net from known netlists and use the machine learning method to train multiple detection models according to the trigger modes. The detection models are used to identify suspicious trigger nets from the netlist of the integrated circuit under detection, and score each net in terms of suspiciousness value. By flagging the top 2% suspicious nets with the highest suspiciousness values, we shall be able to detect majority hardware Trojans, with an average accuracy rate of 96%.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115227673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Lightweight Delay-based Authentication Scheme for DMA Attack Mitigation 基于延迟的DMA攻击缓解轻量级认证方案

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424262

Yutian Gui, A. Siddiqui, Geraldine Shirley Nicholas, Marcus Hughes, F. Saqib

引用次数: 1

A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects 面向异构芯片互连的可重构异步SERDES

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424296

Jainaveen Sundaram, S. Gopal, T. Thomas, Edward Burton, E. Ramirez

引用次数: 1

Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation 基于SRAM的内存和近内存计算的趋势和机遇

2021 22nd International Symposium on Quality Electronic Design (ISQED) Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424263

S. Srinivasa, A. Ramanathan, Jainaveen Sundaram, Dileep Kurian, S. Gopal, Nilesh Jain, Anuradha Srinivasan, R. Iyer, N. Vijaykrishnan, T. Karnik

{"title":"Trends and Opportunities for SRAM Based In-Memory and Near-Memory Computation","authors":"S. Srinivasa, A. Ramanathan, Jainaveen Sundaram, Dileep Kurian, S. Gopal, Nilesh Jain, Anuradha Srinivasan, R. Iyer, N. Vijaykrishnan, T. Karnik","doi":"10.1109/ISQED51717.2021.9424263","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424263","url":null,"abstract":"Changes in application trends along with increasing number of connected devices have led to explosion in the amount of data being generated every single day. Computing systems need to efficiently process these huge amounts of data and generate results, classify objects, stream high quality videos and so on. In-Memory Computing and Near-Memory Computing have been emerged as the popular design choices to address the challenges in executing the above-mentioned tasks. Through In-Memory Computing, SRAM Banks can be repurposed as compute engines while performing Bulk Boolean operations. Near-Memory techniques have shown promise in improving the performance of Machine learning tasks. By carefully understanding the design we describe the opportunities towards amalgamating both these design techniques for obtaining further performance enhancement and achieving lower power budget while executing fundamental Machine Learning primitives. In this work, we take the example of Sparse Matrix Multiplication, and design an I-NMC accelerator which speeds up the index handling by 10x-60x and 10x-70x energy efficiency based on the workload dimensions as compared with non I-NMC solution occupying just 1% of the overall hardware area.","PeriodicalId":123018,"journal":{"name":"2021 22nd International Symposium on Quality Electronic Design (ISQED)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129955567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2