发布求助
文献互助 智能选刊 最新文献

10th IEEE International NEWCAS Conference最新文献

筛选
英文 中文
Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors 采用双极性碳纳米管晶体管设计的三元内容可寻址存储单元
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329046
Kundan Nepal
{"title":"Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors","authors":"Kundan Nepal","doi":"10.1109/NEWCAS.2012.6329046","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329046","url":null,"abstract":"This paper explores the use of carbon nanotube transistors and their ambipolar properties to create ternary content addressable memory (CAM) cells. We show designs and simulation results for a traditional ternary cell created using two storage elements as well as an area efficient (up to 31% lower) truly 3-valued ternary cell.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121724297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Backside-illumination 14µm-pixel QVGA time-of-flight CMOS imager 背面照明14µm像素QVGA飞行时间CMOS成像仪
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329022
M. Oh, H. Kong, Han Soo Lee, Kyung Il Kim, Kwanghyuk Bae, Soo Bang Kim, Sung Kwan Kim, Moosup Lim, J. Ahn, Tae-Chan Kim, G. Hiroshige, S. Kim, D. Min, Yongjei Lee
{"title":"Backside-illumination 14µm-pixel QVGA time-of-flight CMOS imager","authors":"M. Oh, H. Kong, Han Soo Lee, Kyung Il Kim, Kwanghyuk Bae, Soo Bang Kim, Sung Kwan Kim, Moosup Lim, J. Ahn, Tae-Chan Kim, G. Hiroshige, S. Kim, D. Min, Yongjei Lee","doi":"10.1109/NEWCAS.2012.6329022","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329022","url":null,"abstract":"This paper presents a BSI(backside-illumination) 14μm-pixel QVGA CMOS image sensor SOC(System On a Chip) measuring TOF(Time-Of-Flight) by 20MHz-intensity modulation of 850nm-wavelength light. The 34% of overall QE(Quantum Efficiency) at 850nm-wavelength is acquired by BSI structure and optimized micro-lens. The DE(Depth Error) less than 1.5% within 6m is achieved with imaging lens of f/1.2 and LED array of which the optical intensity is 0.6W/m2 at 1m-distance. Additionally, the depth linearity is measured as that the coefficient of determination is equal to 0.9999. In order to operate under background light illumination on a scene, dual CG(Conversion Gain) scheme is implemented in each pixel.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123555934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
PImMS: A self-triggered, 25ns resolution monolithic CMOS sensor for Time-of-Flight and Imaging Mass Spectrometry 一种自触发，25ns分辨率单片CMOS传感器，用于飞行时间和成像质谱
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329065
I. Sedgwick, A. Clark, J. Crooks, R. Turchetta, L. Hill, J. John, A. Nomerotski, R. Pisarczyk, M. Brouard, S. H. Gardiner, E. Halford, J. Lee, M. Lipciuc, C. Slater, C. Vallance, E. Wilman, B. Winter, W. Yuen
{"title":"PImMS: A self-triggered, 25ns resolution monolithic CMOS sensor for Time-of-Flight and Imaging Mass Spectrometry","authors":"I. Sedgwick, A. Clark, J. Crooks, R. Turchetta, L. Hill, J. John, A. Nomerotski, R. Pisarczyk, M. Brouard, S. H. Gardiner, E. Halford, J. Lee, M. Lipciuc, C. Slater, C. Vallance, E. Wilman, B. Winter, W. Yuen","doi":"10.1109/NEWCAS.2012.6329065","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329065","url":null,"abstract":"In this paper, we present the Pixel Imaging Mass Spectrometry (PImMS) sensor, a pixelated Time-of-Flight (TOF) sensor for use in mass spectrometry. The device detects any event which produces a signal above a programmable threshold with a timing resolution of 25ns. Both analogue and digital readout modes are available and all pixels can be individually trimmed to improve noise performance. The pixels themselves contain analogue signal conditioning circuitry as well as complex logic totalling more than 600 transistors. This large number can be achieved without any loss of quantum efficiency thanks to the use of the patented Isolated N-well Monolithic Active Pixels (INMAPS) process. In this paper, we examine the design of the PImMS 1.0 device and its successor PImMS 2.0, a significantly enlarged sensor with several added features. We will also present some initial results from mass spectrometry experiments performed with PImMS 1.0.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128264929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design and implementation of hardware based watermarking solutions for CMOS image sensors 基于硬件的CMOS图像传感器水印解决方案的设计与实现
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329026
Sonjoy Deb Roy, O. Yadid-Pecht
{"title":"Design and implementation of hardware based watermarking solutions for CMOS image sensors","authors":"Sonjoy Deb Roy, O. Yadid-Pecht","doi":"10.1109/NEWCAS.2012.6329026","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329026","url":null,"abstract":"This work presents the design and implementation of hardware based digital watermarking solutions that can insert invisible and semi-fragile watermark into multimedia contents (image or video) captured by CMOS based image sensors, in real time for authentication purposes. The systems are designed to be integrated with the CMOS based camera unit. Starting from our initial JPEG based watermarking design, through an MJPEG one, we will also report on the watermarking solution for the commonly used MPEG encoded video. The current reported system works in real time right after the capturing of video by the CMOS based image sensor. The watermark embedding is processed in the Discrete Cosine Transform (DCT) domain which allows the integration of both watermarking and encoding of the video (or image) into a single system. The hardware based watermarking system described here, works efficiently without high penalty in system power consumption and hardware resources. Moreover, the watermarking rate (watermark generation and embedding) is also high enough to adapt with the frame rate of MPEG-4 video streams in realtime. This new hardware based watermarking system for CMOS based image sensor features minimum video quality degradation and it can withstand certain potential attacks i.e. cover-up attack, cropping, and segment removal from video sequences.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116623725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New design of transient-noise detection circuit with SCR device for system-level ESD protection 基于可控硅器件的系统级ESD瞬态噪声检测电路的新设计
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328961
M. Ker, Wan-Yen Lin
{"title":"New design of transient-noise detection circuit with SCR device for system-level ESD protection","authors":"M. Ker, Wan-Yen Lin","doi":"10.1109/NEWCAS.2012.6328961","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328961","url":null,"abstract":"A new SCR-based transient detection circuit for on-chip protection design against system-level ESD-induced electrical transient disturbance is proposed and verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the new proposed detection circuit can successfully memorize the occurrence of system-level ESD-induced electrical transient events. The detection output can be cooperated with firmware operation to automatically execute system recovery procedure, therefore the immunity of microelectronic systems against system-level ESD test can be effectively improved.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130010171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimized new ADC architecture using ΣΔ modulators for nonlinearly distorted signals 利用ΣΔ调制器对非线性失真信号优化了新的ADC架构
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329002
Dang-Kièn Germain Pham, P. Desgreys, P. Loumeau, T. Ridgers
{"title":"Optimized new ADC architecture using ΣΔ modulators for nonlinearly distorted signals","authors":"Dang-Kièn Germain Pham, P. Desgreys, P. Loumeau, T. Ridgers","doi":"10.1109/NEWCAS.2012.6329002","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329002","url":null,"abstract":"In this paper, a new ADC architecture using bandpass ΣΔ modulators is proposed. It uses the novel concept of residual signal transfer function (RSTF) and of noise band cancellation to digitize nonlinearly distorted signals such as RF power amplifiers outputs. Mathematical analysis and system simulations show the validity of these concepts. We also present a high level design methodology to optimize the actual peak signal-to-noise and the stability of ΣΔ modulators. We provide the result of extensive simulations to help the design of such a converter.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134448577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Ultra-low-power RF transceivers for WBANs in medical applications 超低功耗射频收发器，用于医疗应用的无线局域网
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328977
N. Wu, Qi Zhang
{"title":"Ultra-low-power RF transceivers for WBANs in medical applications","authors":"N. Wu, Qi Zhang","doi":"10.1109/NEWCAS.2012.6328977","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328977","url":null,"abstract":"The paper presents two ultra-low-power ISM band RF transceivers for wireless body area networks (WBANs) in medical applications. Two RF transceivers with an asymmetric architecture are proposed to achieve high energy efficiency according to the asymmetric communication in WBANs. The 2.4 GHz transceiver consists of an OOK receiver (RX) with wake-up circuit (WuRx) and a BFSK/4FSK high speed transmitter (TX) with fast lock-in PLL. The 400 MHz transceiver consists of an OOK RX and a QPSK/8PSK/16QAM TX with a current-reused PLL. Different frequency bands and modulation schemes are adopted in the transceivers to fit different energy-efficient applications. Some novel circuit techniques: asymmetric transceiver architecture, phase-locked loop (PLL) synthesizer with a direct frequency presetting, passive wake-up circuit, and CMOS non-volatile memory (NVM) are used to reduce the power consumption and increase the performance. The transceivers are implemented in 0.18 um RF CMOS process. The max date rate of the TX is 7.5 Mbps with energy efficiency of less than 1 nJ/bit. The RX achieves a sensitivity of -55 dBm at a 100 kbps OOK data rate while consuming just 210 uW power.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114886730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Statistical delay modelling of manufacturing process variations at system level 系统级制造过程变化的统计延迟建模
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328974
Chenxi Ni, G. Russell, A. Bystrov
{"title":"Statistical delay modelling of manufacturing process variations at system level","authors":"Chenxi Ni, G. Russell, A. Bystrov","doi":"10.1109/NEWCAS.2012.6328974","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328974","url":null,"abstract":"Process variation has become a major issue in system performance estimation as the technology feature size continues to decrease. This paper proposes a statistical methodology to bring the process variation effects from transistor level up to system level in terms of circuit delay. A cell library has been built which offers a rapid analysis of process variation effects on system delay performance. As a demonstration vehicle for this technique, the delay distribution of a micropipeline circuit has been simulated using this cell library. The experimental results show that the proposed method is much faster than the traditional SSTA approach by a factor of 50; the results are also compared with Monte Carlo simulation data for validation purposes, and show an acceptable error rate of within 5% and in most cases less than 3%.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132278489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Optimize hardware with fixed-point variable length phase factors 优化硬件与定点可变长度相位因子
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328969
Todd E. Schmuland, M. Jamali, M. Longbrake, P. Buxa
{"title":"Optimize hardware with fixed-point variable length phase factors","authors":"Todd E. Schmuland, M. Jamali, M. Longbrake, P. Buxa","doi":"10.1109/NEWCAS.2012.6328969","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328969","url":null,"abstract":"Fast Fourier Transforms (FFTs) are highly parallel in nature and consist of simple addition, subtraction, and complex rotation operators with phase factors (a.k.a. twiddle factors). With the advent of FPGAs and other reconfigurable seas-of-logic, it is now possible to construct a fully parallel FFT structure where the phase factors are now constants and good targets for hardware optimization. By varying the fixed-point length of the phase factors using phase angle error percentage as a control for the variable length phase factor quantizer, the number of shifted adders required to implement the complex rotation operators can be reduced. Performance comparisons of fixed length and variable length phase factors, along with two quantizer rounding modes, are investigated.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132811900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator 一种采用两级动态d型触发器作为量化噪声传播器的62 db SNDR二阶门控环振荡器TDC
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329013
Keisuke Okuno, T. Konishi, S. Izumi, M. Yoshimoto, H. Kawaguchi
{"title":"A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator","authors":"Keisuke Okuno, T. Konishi, S. Izumi, M. Yoshimoto, H. Kawaguchi","doi":"10.1109/NEWCAS.2012.6329013","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329013","url":null,"abstract":"This paper presents a second-order noise shaping time-to-digital converter (TDC) with two gated ring oscillators (GROs). The oscillating outputs from the GROs are counted and digitized. As a quantization noise propagator (QNP) between the two GROs, two-stage dynamic d-type flipflops (DDFFs) and a NOR gate are adopted. The proposed QNP does not propagate a time error caused by flipflop's metastability to the next GRO, and thus improves its linearity over the conventional masters-lave d-type flipflop. In a standard 65-nm CMOS process, an SNDR of 62-dB is achievable at a sampling rate of 65MS/s.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122132699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信