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Default connection in multi-electrode leads for cardiac pacemakers 心脏起搏器多电极引线的默认连接
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328980
Islam Seoudi, J. Debroux, M. Laflutte, A. Makdissi, Karima Amara, R. D. Molin, A. Amara
{"title":"Default connection in multi-electrode leads for cardiac pacemakers","authors":"Islam Seoudi, J. Debroux, M. Laflutte, A. Makdissi, Karima Amara, R. D. Molin, A. Amara","doi":"10.1109/NEWCAS.2012.6328980","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328980","url":null,"abstract":"Modern pacemakers deliver localized electrical stimuli to the cardiac tissue using electrodes located in the stimulation lead. Recently pacemakers with multiple electrode leads have shown lot of potential in cardiac therapy. However, pacemaker devices have limited lifetime (5 to 7 years), after which it must be surgically replaced potentially by devices not designed to support the operation of multi electrode lead thereby creating compatibility problems. In this paper we present the design and implementation of a chip which addresses these problems. Our solution enlarges our lead compatibility to cover all pacemakers in the market. We discuss and provide solutions to the key challenges of such design in a constrained cardiac environment. Our chip has been manufactured in 0.18 μm technology, occupies 2.2 × 1.75 mm2 area and harvests the stimulation energy to power itself. To the best of our knowledge our study is the first published study of its kind.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125043097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 3.3 GHz class-E power amplifier with 77% PAE utilising GaN HEMT technology 3.3 GHz e类功率放大器，77% PAE，采用GaN HEMT技术
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329040
S. Werner, D. Kalim, R. Negra
{"title":"A 3.3 GHz class-E power amplifier with 77% PAE utilising GaN HEMT technology","authors":"S. Werner, D. Kalim, R. Negra","doi":"10.1109/NEWCAS.2012.6329040","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329040","url":null,"abstract":"High efficiency with high power amplification is of great concern in modern wireless communication systems to increase battery life and reliability. GaN Heterojunction Electron Mobility Transistors (HEMT) have found widespread applications in RF/microwave power amplifiers (PAs) to fulfill these requirements. In this paper, a transmission-line based class-E PA is designed in GaN HEMT technology at 3.3 GHz. The implemented load transformation network (LTN) of the PA separates the DC biasing and the second harmonic termination into two sections as compared to conventional LTN for class-E PAs to attain high efficiency. Measured impedances of the passive LTN are in good agreement with the desired values. Measurement results of the class-E PA show peak power added efficiency (PAE) of 76.9% and peak output power of more than 38.0 dBm, when operated from a 28V supply.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127757049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks 一种兼容FPGA的无线传感器网络异步唤醒接收器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329034
J. Pons, Jean-Jules Brault, Y. Savaria
{"title":"An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks","authors":"J. Pons, Jean-Jules Brault, Y. Savaria","doi":"10.1109/NEWCAS.2012.6329034","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329034","url":null,"abstract":"This paper explores design methods applicable to Wireless Sensors Networks, where low power consumption and energy efficiency are a must. A key component that modulates the power consumption is the main radio. Controlling its use through suitable sleep modes and wake up mechanisms is a significant issue and can be done with a wake-up receiver. But many applications are associated with low fabrication volume where custom integrated circuits are not economical and where FPGAs are the best available solution. In this paper, we explore an asynchronous solution, which permits to decrease the internal activity, thus reducing the power consumption, including that required for clock distribution. We also propose an FPGA implementation of such a wake-up receiver using the NULL Convention Logic™. The overall power consumption of the reported implementation is as low as 5μW at 250 kbps.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127595050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A digital front-end of 16-bit audio delta-sigma DAC with improved CSE method and novel DWA 采用改进的CSE方法和新颖的DWA设计了一种16位音频delta-sigma DAC数字前端
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329009
Jinchen Zhao, Xiaobo Wu, Menglian Zhao
{"title":"A digital front-end of 16-bit audio delta-sigma DAC with improved CSE method and novel DWA","authors":"Jinchen Zhao, Xiaobo Wu, Menglian Zhao","doi":"10.1109/NEWCAS.2012.6329009","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329009","url":null,"abstract":"To achieve area-efficiency and high SNR, a novel digital front-end of a 16-bit audio DAC including a 4-stage interpolator and a 3rd-order delta-sigma (ΣΔ) modulator is proposed. An improved common subexpression elimination (CSE) method is used for implementing the interpolator to save the hardware overhead. And a novel data weighted averaging (DWA) technique named as dual cycle shifted DWA is applied to the 4-bit ΣΔ modulator to reduce the mismatch errors without introducing signal-dependent tones. Implemented in a standard 0.18-μm 1P6M LOGIC salicide process, the proposed design achieves a peak SNR of 103.9-dB and a DR of 104.3-dB, which proves that the proposed work achieves the design goal well.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121227503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Premature edge breakdown prevention techniques in CMOS APD fabrication CMOS APD制造中防止过早边缘击穿的技术
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329027
E. Kamrani, F. Lesage, M. Sawan
{"title":"Premature edge breakdown prevention techniques in CMOS APD fabrication","authors":"E. Kamrani, F. Lesage, M. Sawan","doi":"10.1109/NEWCAS.2012.6329027","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329027","url":null,"abstract":"In this paper we have introduced the most popular applied premature edge breakdown prevention (PEBP) techniques and proposed a new practical and efficient design procedure technique to design a functional avalanche photodiode using standard CMOS process based on our design, simulation and fabrication experiences. The device simulations are used to find the best dimensional values minimizing PEB. Three proposed PEBP techniques are emerged from a systematic study aimed at miniaturization, while optimizing the overall performance. Based on the experimental results gained from the fabrication of a p-well and p-sub guard-rings a new n-well guard-ring PEBP technique is introduced and its performance is evaluated using the device simulation. It exhibits a dark count rate of 1 kHz (with 0.5V excess bias at room temperature), a maximum photon detection probability of 70% at maximum excess bias and 9V breakdown voltage.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124452838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A low power RC time constant auto-tuning circuit for RC-integrators in high linearity continuous-time delta sigma modulators 一种用于高线性连续时间δ σ调制器中RC积分器的低功率RC时间常数自调谐电路
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329011
C. Ouffoue, V. Nguyen, C. Jabbour, H. Fakhoury, P. Loumeau
{"title":"A low power RC time constant auto-tuning circuit for RC-integrators in high linearity continuous-time delta sigma modulators","authors":"C. Ouffoue, V. Nguyen, C. Jabbour, H. Fakhoury, P. Loumeau","doi":"10.1109/NEWCAS.2012.6329011","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329011","url":null,"abstract":"This paper presents the design of a low power RC time constant tuning circuit for high linearity 5th order continuous time Delta Sigma modulator used in LTE-A application with 40 MHz bandwidth. This auto-tuning system contains an analog integrator, a voltage comparator, and a digital tuning engine performed by a clock generator, a register and a counter which generate a control word that sets a programmable capacitors bank to obtain an RC time constant accuracy better than ±2%. It resolves process variations issues which could result in up to ±30% of RC time constant uncertainty and degrade the Delta Sigma modulators SNDR. The system has been designed in a 65 nm CMOS technology with 1.2 V supply voltage and power consumption is less than 200 μW.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122861621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A spectro reflectance camera for in vivo human blood evaluation 一种用于人体内血液评价的光谱反射照相机
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329074
S. Benhammadi, Y. Audet, V. Diaconu
{"title":"A spectro reflectance camera for in vivo human blood evaluation","authors":"S. Benhammadi, Y. Audet, V. Diaconu","doi":"10.1109/NEWCAS.2012.6329074","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329074","url":null,"abstract":"In this paper, we present a new non invasive diagnosing device, the spectroscopy reflectance camera. This device combines the spectro-reflectrometry with a CMOS image sensor to evaluate the oxygen saturation in living organs. This combination is realized by merging an image sensor to an optical fibre linked to a spectrograph. While the image sensor helps targeting precisely the blood vessel to be evaluated, the spectrograph gathers the reflected light spectrum from the vessel. The optical fibre is 50 microns diameter and has one end inserted in the back side of the image sensor. This end reaches the first silicon oxide layer on the component side, which is transparent. The other end is connected to the spectrograph; it transmits the intensity of the reflected light. In order to insert the optical fibre in the image sensor, we propose a process to achieve a highly directional etching technique with high aspect ratio. Also, we present a new image sensor structure allowing the presence of a hole in the center of the pixel array. The presence of the hole adds some design constraints leading to divide a conventional pixel array into four independent sub-arrays, where every pixel is addressed and read out separately.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131484134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A comprehensive study on the power-sensitivity trade-off in TRF receivers TRF接收机功率灵敏度权衡的综合研究
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329041
Shahaboddin Moazzeni, G. Cowan, M. Sawan
{"title":"A comprehensive study on the power-sensitivity trade-off in TRF receivers","authors":"Shahaboddin Moazzeni, G. Cowan, M. Sawan","doi":"10.1109/NEWCAS.2012.6329041","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329041","url":null,"abstract":"There has always been a trade-off between the sensitivity of an RF receiver and its total power consumption meaning that in order to design a receiver with a high sensitivity, more power must be dissipated. However, this inevitable trade-off can be tolerated in applications where only one of these two margins is of interest. For example, ultra-low power receivers in general and wake-up receivers in particular may still be applicable with a sensitivity of better than -70 dBm if the power consumption requirement has been satisfied. We present in this paper a through analytical/graphical approach in order to derive the power-sensitivity characteristics for a general Tuned Radio Frequency receiver based on practical assumptions.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131937100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Systematic comparison of two low-voltage amplifiers using topology matching and performance constraints 采用拓扑匹配和性能约束的两种低压放大器的系统比较
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328997
C. Ferent, A. Doboli
{"title":"Systematic comparison of two low-voltage amplifiers using topology matching and performance constraints","authors":"C. Ferent, A. Doboli","doi":"10.1109/NEWCAS.2012.6328997","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328997","url":null,"abstract":"This paper presents the comparison of two low-voltage amplifiers using a systematic, two step procedure: (i) automated topological matching highlighting common and different signal path structures and symbolic expressions and (ii) constraint extraction and analysis illustrating how dissimilarities between circuits impact relevant performance and showing design flexibility with respect to trade-offs. The obtained comparison is important for understanding benefits and limitations of unique features in designs, for selecting better fitting topologies, and for analog circuit synthesis tools.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123577610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Calibration requires calibration, a case study: Mixed-signal BISC Time-Interleaved ADC 校准需要校准，一个案例研究:混合信号BISC时间交错ADC
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329032
A. Mariano, F. Rivet
{"title":"Calibration requires calibration, a case study: Mixed-signal BISC Time-Interleaved ADC","authors":"A. Mariano, F. Rivet","doi":"10.1109/NEWCAS.2012.6329032","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329032","url":null,"abstract":"Modern electronic systems claim for Analog-to-Digital (A/D) interfaces with strong requirements in terms of resolution and frequency. Among several A/D architectures that intent to achieve these hard specifications, Time-Interleaved Analog-to-Digital Converters (TIADC) arises as a competitive candidate. TIADC offer a higher sampling frequency with suitable moderate power consumption. However, their architecture introduces mismatch errors that affect the resolution of data conversion. Calibration methods permit to reduce significantly the impact of these errors. A possible solution is the insertion of an additional circuitry in the A/D conversion system: a Built-In Self-Calibration (BISC). A BISC system aims to compensate imperfections from the TIADC, such as offset, gain and timing errors. Despite the benefits carried by the BISC, this system also introduces errors in the overall data conversion system. This paper proposes a case study of a mixed-signal BISC TIADC, highlighting the strengths and the weakness of using built-in calibration circuits. Supplementary calibration methods will be explored to mitigate the impact of the BISC and to improve the A/D conversion performance. The debate is open: how calibration systems must be calibrated?","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122896522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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