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Event-driven asynchronous voltage monitoring in energy harvesting platforms 能量收集平台中事件驱动的异步电压监测
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329055
J. Christmann, E. Beigné, C. Condemine, C. Piguet
{"title":"Event-driven asynchronous voltage monitoring in energy harvesting platforms","authors":"J. Christmann, E. Beigné, C. Condemine, C. Piguet","doi":"10.1109/NEWCAS.2012.6329055","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329055","url":null,"abstract":"Achieving high energy efficiency harvesting platforms requires tracking variations of the energy levels. Leveraging energy storage components whose voltage level varies with the state of charge, it becomes efficient to perform voltage monitoring. In this paper, we propose two types of analog-to-digital voltage monitoring interfaces. In both cases, their outputs directly fit asynchronous 4-phases protocol and Quasi Delay Insensitive (QDI) logic. On the one hand, in a passive voltage monitoring scheme, the platform waits for energy-events. Reacting to voltage threshold crossings, data-events are generated and sent to the asynchronous controller. On the other hand, in an active scheme, the platform waits for an asynchronous data-event before evaluating the voltage level. The analog structure is thus included into the asynchronous protocol and provides a controlled voltage monitoring. These innovative structures allow the voltage monitoring power consumption to be under 300 nA at 0.8 V and to be functional in a wide supply voltage range up to 1.8V.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121070270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A tunable and reconfigurable active filter based on distributed structure concept 基于分布式结构概念的可调可重构有源滤波器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329038
L. Kamoun, P. Dueme, J. Plaze, E. Kerhervé, B. Godara
{"title":"A tunable and reconfigurable active filter based on distributed structure concept","authors":"L. Kamoun, P. Dueme, J. Plaze, E. Kerhervé, B. Godara","doi":"10.1109/NEWCAS.2012.6329038","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329038","url":null,"abstract":"The filter presented in this article is an active band-pass filter which center frequency and bandwidth can be tuned. It is composed of channels inserted into a distributed structure, and the frequency agility is obtained by activating one or more of them. The concept is validated with measurements realized on a 3-channel prototype structure implemented in a PPH25 GaAs technology. This filter is tunable throughout the X and Ku bands. This first prototype yields encouraging results: the center frequency can be tuned between 9.7 and 14 GHz, with an average gain of 10 dB throughout this range. The filter occupies 13.5 mm2 of area and consumes 10.5 mA per active stage from a 4V supplying voltage. It is designed for wideband and agile receivers.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116845247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
FPGA-implementation of pipelined neural network for power amplifier modeling fpga实现的流水线神经网络用于功率放大器建模
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328968
Roger Sandrin Ntouné Ntouné, M. Bahoura, Chan-Wang Park
{"title":"FPGA-implementation of pipelined neural network for power amplifier modeling","authors":"Roger Sandrin Ntouné Ntouné, M. Bahoura, Chan-Wang Park","doi":"10.1109/NEWCAS.2012.6328968","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328968","url":null,"abstract":"FPGA-Implementation of pipelined real-valued time-delay neural network (RVTDNN) for power amplifier modeling is presented in this paper. Pipelined and pseudo-conventional RVTDNN architectures are implemented on their parallel forms to exploit the inherent concurrent computing tasks of field programmable gate array (FPGA). The proposed pipelined architecture is based on the delayed back-propagation learning algorithm for adaptive correction of neuron weights and biases. The proposed pipelined RVTDNN has a reduced critical path and an increased maximum operating frequency to 6.5 times faster than pseudo-conventional RVTDNN. Results obtained with both RVTDNN models using a modulated 16-QAM baseband signal are very close to those obtained comparing with the reference model.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116178058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Wireless transceivers for gigabit-per-second communications 用于每秒千兆通信的无线收发器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329077
J. Gorisse, D. Morche, J. Jantunen
{"title":"Wireless transceivers for gigabit-per-second communications","authors":"J. Gorisse, D. Morche, J. Jantunen","doi":"10.1109/NEWCAS.2012.6329077","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329077","url":null,"abstract":"This paper presents a state-of-the-art of wireless transceivers providing Gbps data-rate. This study focuses on the power consumption of such systems and puts it into balance with respect to the data-rate through the energy efficiency and with respect to the communication distance through a new Figure-of-Merit. An analysis of this state-of-the-art is also proposed which gives a new perspective on Gbps wireless systems.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Positive feedback technique for DC-gain enhancement of folded cascode Op-Amps 叠式级联运放直流增益增强的正反馈技术
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329006
Sina Farahmand, H. Shamsi
{"title":"Positive feedback technique for DC-gain enhancement of folded cascode Op-Amps","authors":"Sina Farahmand, H. Shamsi","doi":"10.1109/NEWCAS.2012.6329006","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329006","url":null,"abstract":"In this paper, a novel folded cascode operational amplifier is proposed which improves DC-gain using positive feedback technique. This method does not affect the unity-gain frequency, stability, power dissipation, and output voltage swing of the conventional folded cascode Op-Amp. The proposed Op-Amp was designed in a standard 0.18μm TSMC 1.8V CMOS technology. Simulation results show a DC-gain enhancement of 25dB and 513MHz unity gain bandwidth for the presented Op-Amp. HSPICE simulation results confirm the theoretical estimated improvements.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129906574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
N-path gmC filter modeling and analysis for direct delta-sigma receiver 直接德尔塔-西格玛接收机n路gmC滤波器建模与分析
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329010
Mikko Englund, O. Viitala, J. Ryynänen, K. Koli
{"title":"N-path gmC filter modeling and analysis for direct delta-sigma receiver","authors":"Mikko Englund, O. Viitala, J. Ryynänen, K. Koli","doi":"10.1109/NEWCAS.2012.6329010","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329010","url":null,"abstract":"This paper presents the analysis and a model for obtaining the delta-sigma loop filter coefficients of a direct delta-sigma receiver (DDSR). The analysis is done by modeling a key element of the DDSR, the N-path filter, with an s-plane transfer function in the baseband. The s-plane model includes the most important non-idealities, such as switch resistances and the limited output resistances of the RF-stages. The model allows the designer to approximate the key parameters for DDSR and enables the optimization of the DDSR performance. As an example, the coefficients of a third-order DDSR are obtained by examining the s-plane and the corresponding z-plane signal and quantization noise transfer functions. The results are evaluated with circuit level simulations.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130772968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A frequency-domain study of lock range of harmonic oscillators with multiple injections 多次注入谐振子锁紧范围的频域研究
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328948
F. Yuan, Yushi Zhou
{"title":"A frequency-domain study of lock range of harmonic oscillators with multiple injections","authors":"F. Yuan, Yushi Zhou","doi":"10.1109/NEWCAS.2012.6328948","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328948","url":null,"abstract":"This paper presents a frequency-domain study of the lock range of harmonic oscillators with multiple injections. The intrinsic relation between the lock range of harmonic oscillators with multiple injections and that with a single injection is obtained. We show that harmonic oscillators with multiple injections exhibit a larger lock range as compared with those with single injection if the phases of the injection signals is properly chosen. The findings are validated using LC oscillators with single injection and dual injections designed in IBM 130 nm 1.2 V CMOS technology.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122933980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Self-sorting FFT method eliminating trivial multiplication and suitable for embedded DSP processor 自排序FFT方法消除了繁琐的乘法运算，适合嵌入式DSP处理器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328954
Marwan A. Jaber, D. Massicotte
{"title":"Self-sorting FFT method eliminating trivial multiplication and suitable for embedded DSP processor","authors":"Marwan A. Jaber, D. Massicotte","doi":"10.1109/NEWCAS.2012.6328954","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328954","url":null,"abstract":"The Discrete Fourier Transform (DFT) is a mathematical procedure at the core of processing inside a Digital Signal Processor. Speed and low complexity are crucial in the FFT process; they can be achieved by avoiding trivial multiplications through a proper handling of the input/output data and the twiddle factors. Accordingly, this paper presents an innovative approach for handling the input/output data efficiently by avoiding trivial multiplications. This approach consists of a simple mapping of the three indices (FFT stage, butterfly and element) to the addresses of the input/output data with their corresponding coefficient multiplier. A self-sorting algorithm that reduces the amount of memory accesses to the coefficient multipliers' memory can also reduce the computational load by avoiding all trivial multiplications. Compared with the most-recent work [5], performance evaluation in terms of the number of cycles on the general-purpose TMS320C6416 DSP shows a reduction of 29% (FFT of size 4096) and a 50% memory reduction to stock twiddle factors. The algorithm has also shown a speed gain of 24% on the FFTW platform for a FFT of size 4096.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115048356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a miniaturized UWB antenna optimized for implantable neural recording systems 用于植入式神经记录系统优化的小型化超宽带天线设计
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329018
H. Bahrami, B. Gosselin, L. Rusch
{"title":"Design of a miniaturized UWB antenna optimized for implantable neural recording systems","authors":"H. Bahrami, B. Gosselin, L. Rusch","doi":"10.1109/NEWCAS.2012.6329018","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329018","url":null,"abstract":"Ultra-wideband (UWB) short-range communication systems are valuable in medical technology, particularly for implanted devices, due to their low-power consumption, low cost, and high data rates. Several emerging medical applications require that a miniature data acquisition device be implanted in the head to extract and wirelessly communicate brain activity to other devices. In such applications the antennas, a key component in a wireless implanted device, require extreme biocompatibility and limited size. This paper presents the design of a miniaturized UWB monopole microstrip antenna that is electrically suitable for implantation in the human head. The antenna is fed by a microstrip line on an FR4 substrate, has a size limited to 12mm×12mm, and is optimized against the effects of biological tissues. Optimization is performed numerically with HFSS. The return loss, radiation pattern and specific absorption rate (SAR) performance of the antenna are simulated and compared for three antenna sizes. Based on these results, a suitable UWB antenna is proposed for operation in an implanted neural recording device.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114354990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter 基于混合信号笛卡尔反馈训练的3G纯差发射机数字预失真设计
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328964
W. Sanaa, B. Gal, D. Dallet, C. Rebai, N. Deltimple, D. Belot, E. Kerhervé
{"title":"New digital predistortion design based on mixed-signal cartesian feedback training for 3G homodyne transmitter","authors":"W. Sanaa, B. Gal, D. Dallet, C. Rebai, N. Deltimple, D. Belot, E. Kerhervé","doi":"10.1109/NEWCAS.2012.6328964","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328964","url":null,"abstract":"In this paper, a smart adaptive RF power amplifier linearization technique is presented. We invest a Mixed-Signal Cartesian Feedback Loop design to train an embedded Random Access Memory in order to overcome digital-stage latency and bandwidth limitation. The new design consists of a traditional analog stage including filters, I/Q modulator, feedback I/Q demodulator and an improved digital stage which adjusts the phase misalignment around the loop and updates the RAM. We used a not fully-pipelined CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. We implemented this design for the UMTS standard using ASIC 65nm low power technology. We reached 230 MHz with system power consumption less than 6 mw which is better than a fully analog system (8.8 mW).","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126536544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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