Self-sorting FFT method eliminating trivial multiplication and suitable for embedded DSP processor

Abstract

The Discrete Fourier Transform (DFT) is a mathematical procedure at the core of processing inside a Digital Signal Processor. Speed and low complexity are crucial in the FFT process; they can be achieved by avoiding trivial multiplications through a proper handling of the input/output data and the twiddle factors. Accordingly, this paper presents an innovative approach for handling the input/output data efficiently by avoiding trivial multiplications. This approach consists of a simple mapping of the three indices (FFT stage, butterfly and element) to the addresses of the input/output data with their corresponding coefficient multiplier. A self-sorting algorithm that reduces the amount of memory accesses to the coefficient multipliers' memory can also reduce the computational load by avoiding all trivial multiplications. Compared with the most-recent work [5], performance evaluation in terms of the number of cycles on the general-purpose TMS320C6416 DSP shows a reduction of 29% (FFT of size 4096) and a 50% memory reduction to stock twiddle factors. The algorithm has also shown a speed gain of 24% on the FFTW platform for a FFT of size 4096.