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A low-power digitally programmable impulse radio ultra wideband transmitter with pulse shape control 具有脉冲形状控制的低功耗数字可编程脉冲无线电超宽带发射机
10th IEEE International NEWCAS Conference Pub Date : 2012-10-11 DOI: 10.1109/NEWCAS.2012.6329075
Anh-kiet Vuong, Alexandre Desmarais, A. Bounif, D. Deslandes, F. Nabki
{"title":"A low-power digitally programmable impulse radio ultra wideband transmitter with pulse shape control","authors":"Anh-kiet Vuong, Alexandre Desmarais, A. Bounif, D. Deslandes, F. Nabki","doi":"10.1109/NEWCAS.2012.6329075","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329075","url":null,"abstract":"This paper presents a digitally programmable transmitter for ultra-wideband impulse radio using on-off keying modulation scheme. The circuit can generate pulse widths ranging from 600 ps to 1.5 ns that can be spectrally centered at frequencies ranging from 3.9 GHz to 9.3 GHz. The system allows for digital control of the transmitted power spectrum shape in order to deal with varying transmission environments. The entire transmitter is power cycled, operating from a 1.2 V supply, and consuming a simulated power as low as 0.9 mW at a 10 Mbps data rate.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128715798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 8-segmented 256×512 CMOS image sensor for processing element-coupled unified system in machine vision application 一种用于处理机器视觉中元素耦合统一系统的8段256×512 CMOS图像传感器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329023
T. Otaka, T. Yamasaki, T. Hamamoto
{"title":"An 8-segmented 256×512 CMOS image sensor for processing element-coupled unified system in machine vision application","authors":"T. Otaka, T. Yamasaki, T. Hamamoto","doi":"10.1109/NEWCAS.2012.6329023","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329023","url":null,"abstract":"A CMOS image sensor whose focal plane is split into 8 segments is presented. The proposed architecture adjusts imaging parameters on a segmented base that consists of 128×128 pixels. Each segment is coupled to an external processing engine, which enables faster readout and real-time processing as well as co-operation among the segments regardless of the pixel count. Based on these characteristics, the architecture can provide an excellent unified imaging and processing system that is especially beneficial for machine vision applications. A chip was fabricated using a 0.18-μm 1P5M standard CMOS process and the sensor was demonstrated to achieve individual frame rate and exposure time control with <;0.04% column fixed pattern noise (FPN) and <;0.11% temporal noise.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"69 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120970162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications 一种将基于SDM-TDM的电路交换与分组交换相结合的混合NoC，用于实时应用
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328945
A. K. Lusala, J. Legat
{"title":"A hybrid NoC combining SDM-TDM based circuit-switching with packet-switching for real-time applications","authors":"A. K. Lusala, J. Legat","doi":"10.1109/NEWCAS.2012.6328945","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328945","url":null,"abstract":"This paper proposes a hybrid Network-on-Chip “NoC” which takes advantage of the best of packet switching and circuit-switching in order to handle efficiently both best-effort and streaming traffics generated by real-time applications. The proposed hybrid NoC consists of two sub-networks: a circuit-switched sub-network and a packet-switched sub-network. The circuit-switched sub-network combines Spatial Division Multiplexing “SDM” and Time Division Multiplexing “TDM” in order to increase path diversity in the NoC and to improve resources usage, in this way, quality of service is easily provided for streaming traffic while the packet-switched sub-network handles the best-effort traffic. A 7*7 2D mesh NoC is built and simulated. Simulation results show that this approach allows an increase of the probability of establishing paths through the NoC, reducing thereby contention in the NoC with a reasonable hardware cost as shown in synthesis results.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121115737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications 用于神经信号记录应用的160 nW 25 kS/s 9位SAR ADC
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329072
A. Do, C. Lam, Y. S. Tan, K. Yeo, J. Cheong, X. Zou, Lei Yao, Kuang-Wei Cheng, M. Je
{"title":"A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications","authors":"A. Do, C. Lam, Y. S. Tan, K. Yeo, J. Cheong, X. Zou, Lei Yao, Kuang-Wei Cheng, M. Je","doi":"10.1109/NEWCAS.2012.6329072","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329072","url":null,"abstract":"This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal recording applications. The ADC is powered by a single supply voltage of 1V to comply with other digital processing units on the same chip. The proposed ADC has one common-mode DC input of 0.5V thus offering a full-range sampling with only one pair of PMOS input transistors in the latched comparator. A versatile digital interface block is implemented to translate external control signals to internally useful Sample-and-Hold (S/H) commands, allowing a flexible S/H duration to match with the driving strength of the input buffer. To realize an ultra low-power performance, all digital blocks and the comparator are carefully optimized. At the same time, split-cap architecture with an attenuation cap is used to minimize area and to further reduce the power consumption. Our simulation shows that the proposed SAR archives 8.5 ENOB while consuming only 160 nW.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122349586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
VHDL-AMS model of an injection locked VCO 注射锁定VCO的VHDL-AMS模型
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328947
Q. Beraud-Sudreau, O. Mazouffre, M. Pignol, L. Baguena, C. Neveu, J. Bégueret, T. Taris
{"title":"VHDL-AMS model of an injection locked VCO","authors":"Q. Beraud-Sudreau, O. Mazouffre, M. Pignol, L. Baguena, C. Neveu, J. Bégueret, T. Taris","doi":"10.1109/NEWCAS.2012.6328947","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328947","url":null,"abstract":"A VHDL-AMS model of an injection locked voltage controlled oscillator is presented in this paper. The model is valid for any harmonic of the synchronization signal. Properties such as locking-range, bandwidth and settling time are taken into account. The model is used in mixed simulations to reduce the computation time. A comparison with a schematic LC oscillator shows very good correlation.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122769046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Varactor-tuned active miniature notch filter 变容管调谐有源微型陷波滤波器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328958
R. Lababidi, S. Bourdel, J. Gaubert, A. Louzir, J. Robert, Jean- Yves Le Naour, D. Tong, J. Lintignat, B. Jarry, B. Barelaud
{"title":"Varactor-tuned active miniature notch filter","authors":"R. Lababidi, S. Bourdel, J. Gaubert, A. Louzir, J. Robert, Jean- Yves Le Naour, D. Tong, J. Lintignat, B. Jarry, B. Barelaud","doi":"10.1109/NEWCAS.2012.6328958","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328958","url":null,"abstract":"In this paper a novel tunable miniature active notch filter based on short circuited quarter-wavelength resonator is presented. This simple filter topology uses tunable Active Capacitance (AC) circuit and serves for trial purposes which are described below. Thanks to the use of a varactor diode in parallel within the AC circuit which allows a simultaneous tuning of the notch central frequency and depth whilst maintaining an electrically stable filter. Experimental prototypes based on conventional discrete surface mount components and assembled on a low-cost FR4 substrate have been built up in order to prove this new concept.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122476862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transconductance/drain current based distortion analysis for analog CMOS integrated circuits 基于跨导/漏极电流的模拟CMOS集成电路畸变分析
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328956
J. Ou, F. Farahmand
{"title":"Transconductance/drain current based distortion analysis for analog CMOS integrated circuits","authors":"J. Ou, F. Farahmand","doi":"10.1109/NEWCAS.2012.6328956","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328956","url":null,"abstract":"This paper proposes a technique to analyze distortion in analog CMOS integrated circuits. The proposed technique captures a transistor's nonlinearity using a two-dimensional Taylor series with coefficients that depend on the transconductance-to-current ratio (g<sub>m</sub>/I<sub>D</sub>) of a transistor. To explore the effectiveness of the proposed technique, a common-source amplifier is designed. The harmonics of the amplifier are calculated using both the g<sub>m</sub>/I<sub>D</sub> technique and Cadence's periodic steady state (PSS) analysis over a wide range of g<sub>m</sub>/I<sub>D</sub>. The results indicate a close match (i.e. a discrepancy less than 2 dB from g<sub>m</sub>/I<sub>D</sub>=8 to 30) and show that the proposed technique can indeed be incorporated in a g<sub>m</sub>/I<sub>D</sub> design flow.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122623737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Remote powering realization for smart orthopedic implants 智能骨科植入物的远程供电实现
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329071
Oguz Atasoy, C. Dehollain
{"title":"Remote powering realization for smart orthopedic implants","authors":"Oguz Atasoy, C. Dehollain","doi":"10.1109/NEWCAS.2012.6329071","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329071","url":null,"abstract":"This paper presents a remote powering realization for smart orthopedic implants with a full-wave rectifier and a voltage doubler. The measured power efficiency of the rectifier at 13.56 MHz is 80% for an output power of 20 mW with 2.2 V output. The rectifier consists of two cross coupled PMOS transistors, and two NMOS switches with two comparators. The power efficiency of the voltage doubler is measured to be higher than 85% for output powers from 2 mW to 20 mW. Both circuits are fabricated by using 0.18 μm standard CMOS process. The remote powering is realized by using two spiral coils and a class-E type power amplifier working at 13.56 MHz.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121165784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Highly reconfigurable single-ended low noise amplifier for software defined radio applications 用于软件无线电应用的高度可重构的单端低噪声放大器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329078
R. Beare, C. Plett, J. Rogers
{"title":"Highly reconfigurable single-ended low noise amplifier for software defined radio applications","authors":"R. Beare, C. Plett, J. Rogers","doi":"10.1109/NEWCAS.2012.6329078","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329078","url":null,"abstract":"A reconfigurable low noise amplifier with variable gain, bandwidth and center frequency is described. In order to achieve this degree of reconfigurability, this amplifier employs variable-bias active shunt feedback input matching, with a switchable capacitive load and a Q-enhancing negative gm circuit in parallel with the load. This design also features a noise cancelling technique, which helps to eliminate noise contributions from the primary gain FETs and simultaneously enhance the gain. This design was built on IBM's CMOS 0.13μm process through MOSIS and was designed for a 1.2V supply. This LNA has a min-to-max 3dB bandwidth ratio of approximately 3.1 while achieving a noise figure as low as 2.5dB, less than -10dB return loss, and IIP3 as high as -0.9dBm at low gain.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116294191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Residue-weighted number conversion for moduli set {22n − 1, 22n+1 − 1, 2n} using signed-digit number 模集{22n−1,22n +1−1,2n}的残差加权带符号数转换
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328943
Changjun Jiang, Shugang Wei
{"title":"Residue-weighted number conversion for moduli set {22n − 1, 22n+1 − 1, 2n} using signed-digit number","authors":"Changjun Jiang, Shugang Wei","doi":"10.1109/NEWCAS.2012.6328943","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328943","url":null,"abstract":"By introducing a signed-digit (SD) number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new residue-to-binary conversion algorithm for three-moduli set {22n - 1, 22n+1 - 1, 2n} using the SD number residue addition is proposed. Based on the proposed algorithm, the converter can be designed with only four high-speed SD adders. The comparison of the proposed converter using SD number arithmetic with the converter using binary arithmetic yields more efficient both in terms of area and time.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114728967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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