Transconductance/drain current based distortion analysis for analog CMOS integrated circuits

Abstract

This paper proposes a technique to analyze distortion in analog CMOS integrated circuits. The proposed technique captures a transistor's nonlinearity using a two-dimensional Taylor series with coefficients that depend on the transconductance-to-current ratio (g_m/I_D) of a transistor. To explore the effectiveness of the proposed technique, a common-source amplifier is designed. The harmonics of the amplifier are calculated using both the g_m/I_D technique and Cadence's periodic steady state (PSS) analysis over a wide range of g_m/I_D. The results indicate a close match (i.e. a discrepancy less than 2 dB from g_m/I_D=8 to 30) and show that the proposed technique can indeed be incorporated in a g_m/I_D design flow.