{"title":"An 8-segmented 256×512 CMOS image sensor for processing element-coupled unified system in machine vision application","authors":"T. Otaka, T. Yamasaki, T. Hamamoto","doi":"10.1109/NEWCAS.2012.6329023","DOIUrl":null,"url":null,"abstract":"A CMOS image sensor whose focal plane is split into 8 segments is presented. The proposed architecture adjusts imaging parameters on a segmented base that consists of 128×128 pixels. Each segment is coupled to an external processing engine, which enables faster readout and real-time processing as well as co-operation among the segments regardless of the pixel count. Based on these characteristics, the architecture can provide an excellent unified imaging and processing system that is especially beneficial for machine vision applications. A chip was fabricated using a 0.18-μm 1P5M standard CMOS process and the sensor was demonstrated to achieve individual frame rate and exposure time control with <;0.04% column fixed pattern noise (FPN) and <;0.11% temporal noise.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"69 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"10th IEEE International NEWCAS Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2012.6329023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A CMOS image sensor whose focal plane is split into 8 segments is presented. The proposed architecture adjusts imaging parameters on a segmented base that consists of 128×128 pixels. Each segment is coupled to an external processing engine, which enables faster readout and real-time processing as well as co-operation among the segments regardless of the pixel count. Based on these characteristics, the architecture can provide an excellent unified imaging and processing system that is especially beneficial for machine vision applications. A chip was fabricated using a 0.18-μm 1P5M standard CMOS process and the sensor was demonstrated to achieve individual frame rate and exposure time control with <;0.04% column fixed pattern noise (FPN) and <;0.11% temporal noise.