Premature edge breakdown prevention techniques in CMOS APD fabrication

Abstract

In this paper we have introduced the most popular applied premature edge breakdown prevention (PEBP) techniques and proposed a new practical and efficient design procedure technique to design a functional avalanche photodiode using standard CMOS process based on our design, simulation and fabrication experiences. The device simulations are used to find the best dimensional values minimizing PEB. Three proposed PEBP techniques are emerged from a systematic study aimed at miniaturization, while optimizing the overall performance. Based on the experimental results gained from the fabrication of a p-well and p-sub guard-rings a new n-well guard-ring PEBP technique is introduced and its performance is evaluated using the device simulation. It exhibits a dark count rate of 1 kHz (with 0.5V excess bias at room temperature), a maximum photon detection probability of 70% at maximum excess bias and 9V breakdown voltage.