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A statistically optimal macromodeling framework with application in process variation analysis of MEMS devices 统计最优宏观建模框架及其在MEMS器件工艺变化分析中的应用
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328996
Bin Wu
{"title":"A statistically optimal macromodeling framework with application in process variation analysis of MEMS devices","authors":"Bin Wu","doi":"10.1109/NEWCAS.2012.6328996","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328996","url":null,"abstract":"Macromodels are used extensively in circuit and process analysis for higher computation efficiency, and better insight into system behaviors. A statistically optimal and elegant framework for macro-modeling is proposed in this paper, which can successfully handle the modeling challenges created by the highly customized fabrication/design paradigm of MEMS devices. Without requirements for a priori knowledge and experience of fast emerging and highly diversified MEMS fabrication and design style, the proposed framework can adapt to arbitrary distribution and correlation by optimally scaling the order and dimension of the process variation models for trade-off between accuracy and efficiency. The effectiveness of the proposed framework is demonstrated by process variation modeling and analysis of MEMS devices.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115060815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Symbolic nodal analysis of analog integrated circuits using pathological elements 使用病理元件的模拟集成电路符号节点分析
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328981
E. Tlelo-Cuautle, C. Sánchez-López, S. Tan
{"title":"Symbolic nodal analysis of analog integrated circuits using pathological elements","authors":"E. Tlelo-Cuautle, C. Sánchez-López, S. Tan","doi":"10.1109/NEWCAS.2012.6328981","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328981","url":null,"abstract":"Improvements in analog signal processing applications require the selection of adequate active devices. However, each kind of active device offers different port-characteristics. For instance, the parasitic elements play an important role in selecting the best one for a given application. Symbolic nodal analysis is a useful tool to derive electrical characteristics of analog circuits, but compact models for the active devices are required to generate small matrices and analytical expressions. That way, this paper shows the usefulness of using pathological elements to generate behavioral models including dominant parasitic elements. The proposed approach is useful for the selection of active devices in analog design and synthesis procedures.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123130065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An effective method to use GPU for rectangle packing 一种利用GPU进行矩形填充的有效方法
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328973
M. Kataoka, Shuji Tsukiyamia, T. Kambe, M. Fukui
{"title":"An effective method to use GPU for rectangle packing","authors":"M. Kataoka, Shuji Tsukiyamia, T. Kambe, M. Fukui","doi":"10.1109/NEWCAS.2012.6328973","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328973","url":null,"abstract":"As useful software tools for GPU (Graphics Processing Unit) have been provided, GPGPU (General Purpose computing on GPU) becomes popular recently. However, the usage of GPU in the field of CAD algorithm for VLSI has not been large yet. The reason of this is that algorithms in this field have a tendency such that they must change operations of the next step according to the result of the current step. Hence, introduction of parallelism is not easy. In this paper, we consider rectangle packing problem which is important to VLSI floorplan, and propose an algorithm which can employ GPU effectively. The algorithm is obtained by improving defects of temperature parallel simulated annealing algorithm. Experimental results for benchmark data show its effectiveness.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122726031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A bandwidth enhancement technique for CMOS TIAs driven by large photodiodes 一种由大型光电二极管驱动的CMOS TIAs的带宽增强技术
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329049
M. H. Taghavi, L. Belostotski, J. Haslett
{"title":"A bandwidth enhancement technique for CMOS TIAs driven by large photodiodes","authors":"M. H. Taghavi, L. Belostotski, J. Haslett","doi":"10.1109/NEWCAS.2012.6329049","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329049","url":null,"abstract":"A new method of enhancing the bandwidth of a conventional series-peaked transimpedance amplifier (TIA) driven by a large photodiode is introduced. It is shown that by using N identical TIAs in parallel the circuit bandwidth can be significantly improved. The advantage of the proposed technique is in its ability to provide large bandwidth enhancements in multi-GHz frequency ranges even when photodiode capacitance is large, without a noticeable increase in TIA core circuit area. This technique is supported by a design example simulated in a 0.13μm standard CMOS technology. Simulation results show a 3dB bandwidth of 26GHz with 0.5pF photodiode capacitance, a transimpedance gain of 51dBΩ and group delay of 33.5±4ps. The proposed technique shows an overall bandwidth enhancement ratio of 3.25 with less than 0.1dB gain ripple resulting in higher bandwidth enhancement than previously reported for large photodiode capacitances.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122930848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A new discriminator for a low-power capacitor-less FSK demodulator for biomedical implants 一种用于生物医学植入物的低功率无电容FSK解调器的鉴别器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329015
Mohammad Salahshoor, S. Mirbozorgi, A. Arian, S. Naseh
{"title":"A new discriminator for a low-power capacitor-less FSK demodulator for biomedical implants","authors":"Mohammad Salahshoor, S. Mirbozorgi, A. Arian, S. Naseh","doi":"10.1109/NEWCAS.2012.6329015","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329015","url":null,"abstract":"Many implantable micro-stimulator systems have been proposed in recent years. Communications between the implanted device and outside world is done through an inductive link, which is also used for delivering to the circuit the power required for its operation. Reducing the power consumption and chip area are the key issues in this field. This paper presents a new low power C-less (no capacitor) FSK demodulator which can be used in implantable biomedical devices. The demodulator circuit derives the serial data output and a constant frequency clock from the input FSK carrier. Demodulation procedure is based on the pulse-shrinking principle, in which the pulse width shrinks in successive stages. The circuit is designed and simulated using a commercial 0.18μm CMOS technology. The power consumption of the designed circuit is 42μw from a 1.8 volt power supply with a bit rate of 5Mbps.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125547412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A CMOS-compatible, neuro-transistor array with monolithically-integrated circuit for studying cultured neuronal networks 用于研究培养神经元网络的单片集成电路的cmos兼容神经晶体管阵列
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329017
Hsiang-Chiu Wu, Sheng-Jen Chang, Hsin Chen
{"title":"A CMOS-compatible, neuro-transistor array with monolithically-integrated circuit for studying cultured neuronal networks","authors":"Hsiang-Chiu Wu, Sheng-Jen Chang, Hsin Chen","doi":"10.1109/NEWCAS.2012.6329017","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329017","url":null,"abstract":"In-plan microelectrode arrays have been proven to be useful tools for studying the connection and functions of neural tissues. But the number of electrodes is limited by the complex integration between sensors and signal-processing circuits. This paper presents a single-chip neural-electronic interface integrating the oxide-semiconductor filed effect transistors (OSFETs) with the signal-processing circuits. The chip is fabricated in the standard TSMC 0.35μm process, and then by die-level CMOS post process.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121059119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
System modelling of an integrated hysteretic controlled DC-DC converter 集成滞回控制DC-DC变换器的系统建模
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329033
S. Dietrich, H. Sandner, F. Vanselow, R. Wunderlich, S. Heinen
{"title":"System modelling of an integrated hysteretic controlled DC-DC converter","authors":"S. Dietrich, H. Sandner, F. Vanselow, R. Wunderlich, S. Heinen","doi":"10.1109/NEWCAS.2012.6329033","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329033","url":null,"abstract":"Modelling of system components gains more and more interest in the design flow of integrated analog circuits. Digital parts are well described using e.g. Matlab Simulink or VHDL. On the other hand, analog circuits are complex to model and, therefore, its modeling is time consuming due to missing simulation speed-up or accuracy. Nevertheless, as system complexity rises and transistor level simulations nearly become impossible, adequate models of large integrated analog circuits, like DC-DC converters, are essential. This paper deals with a practical solution to model an integrated, hysteretic controlled DC-DC buck converter. The well known Texas Instruments TPS 62620 is used as an example. The consistency between the modelled chip and the datasheet is shown, while a simulation speed-up of about 30 has been achieved.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123810724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modified TSPC clock dividers for higher frequency division by 3 and lower power operation 改进的TSPC时钟分频器，用于更高频率的3分频和更低的功率操作
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329050
Jerry Lam, C. Plett
{"title":"Modified TSPC clock dividers for higher frequency division by 3 and lower power operation","authors":"Jerry Lam, C. Plett","doi":"10.1109/NEWCAS.2012.6329050","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329050","url":null,"abstract":"This paper presents two novel modifications to the conventional true single-phase clock (TSPC) divide-by-2 clock divider. In the first variation, the maximum frequency of operation is carefully increased beyond its normal frequency of operation. This limits the time certain nodes have to respond and causes an additional clock cycle to be skipped, resulting in division by three. Simulation results predict an increase in maximum frequency range of 2 to 3 GHz, and the robustness of this mode of operation is demonstrated in measured results. The second variation emulates this cycle skipping behavior at lower frequencies by the addition of a series switch in the discharge path of a node as well as the circuitry needed to control this switch. A total of eight additional transistors are added to turn the divide by two circuit into a variable 2/3-divider and is shown in simulation to consume up to 30% less power than a conventional variable divider.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127081336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An improved BCD adder using 6-LUT FPGAs 采用6-LUT fpga的改进BCD加法器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328944
Shuli Gao, D. Al-Khalili, N. Chabini
{"title":"An improved BCD adder using 6-LUT FPGAs","authors":"Shuli Gao, D. Al-Khalili, N. Chabini","doi":"10.1109/NEWCAS.2012.6328944","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328944","url":null,"abstract":"The need for high performance decimal arithmetic is required in many applications. Using binary system to process decimal numbers tends to be costly in terms of area and speed. Hence, there is a demand to realize decimal operations efficiently. In this paper, an improved approach to implement decimal addition is proposed. A hardware implementation of this arithmetic function is developed based on 6-input LUTs and the fast carry chains. In our proposed approach, a new architecture of a BCD adder is presented with emphasis on critical path delay reduction. The adder architecture has been implemented on Xilinx Virtex-6 FPGA for operand sizes from 2 to 18 digits. Our design has outperformed other approaches in terms of area and delay. On average, the delay reduction is 13.1% and LUT saving is 28.9% compared to a conventional BCD adder.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122376720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An UWB transmitter with power cycling and support for multiple modulation schemes 具有功率循环和支持多种调制方案的UWB发射机
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329076
R. Hamdi, Aniss Belarbi, M. Larbi, D. Deslandes, F. Nabki
{"title":"An UWB transmitter with power cycling and support for multiple modulation schemes","authors":"R. Hamdi, Aniss Belarbi, M. Larbi, D. Deslandes, F. Nabki","doi":"10.1109/NEWCAS.2012.6329076","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329076","url":null,"abstract":"A reconfigurable ultra-wideband transmitter using 0.13 μm CMOS technology is presented. The transmitter supports three different modulation schemes: binary phase shift keying, transmitted reference binary phase shift keying and on-off keying. The circuit contains glitch generators that modulate an oscillator combined with a power cycling controller which reduces the power consumption. The simulated output center frequency can be adjusted from 4 to 9 GHz and the transmitter achieves data rates ranging from 1 to 100 Mbps with a power consumption as low as 200 μW at 1 Mbps.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130344892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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