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Stochastic chase decoder for reed-solomon codes 芦苇-所罗门码的随机追逐解码器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328942
Romain Heloir, Camille Leroux, S. Hemati, M. Arzel, W. Gross
{"title":"Stochastic chase decoder for reed-solomon codes","authors":"Romain Heloir, Camille Leroux, S. Hemati, M. Arzel, W. Gross","doi":"10.1109/NEWCAS.2012.6328942","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328942","url":null,"abstract":"This paper presents a hardware implementation of a soft-decision Reed-Solomon (RS) decoder, based on the stochastic Chase algorithm. This decoder achieves a coding gain of at least 0.45 dB at FER=10-4 for the well-known RS(255,239) code. To the best of our knowledge this is the highest reported coding gain for a hardware implementation of soft-decision RS(255,239) decoder. The decoder is implemented on a Virtex-5 FPGA and works at 800 Mb/s. The proposed decoder has a flexible architecture and is well suited for applications requiring different throughputs and decoding performance.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134002017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Replica bit-line technique for embedded multilevel gain-cell DRAM 嵌入式多电平增益单元DRAM的复制位线技术
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328960
M. U. Khalid, P. Meinerzhagen, A. Burg
{"title":"Replica bit-line technique for embedded multilevel gain-cell DRAM","authors":"M. U. Khalid, P. Meinerzhagen, A. Burg","doi":"10.1109/NEWCAS.2012.6328960","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328960","url":null,"abstract":"Multilevel gain-cell DRAMs are interesting to improve the area-efficiency of modern fault-tolerant systems-on-chip implemented in deep-submicron CMOS technologies. This paper addresses the problem of long access times in such multilevel gain-cell DRAMs, which are further aggravated by process parameter variations. A replica bit-line (BL) technique, previously proposed for SRAM, is adapted to speed up the multilevel read operation at a negligible area-increase. Moreover, the same replica column is used to improve the write access time. An 8-kb DRAM macro implemented in 90-nm CMOS technology shows that the replica column is able to successfully track die-to-die process, voltage, and temperature variations to generate control signals with optimum delay. Finally, Monte-Carlo simulations show that a small timing margin of 100 ps is sufficient to also cope with within-die process variations.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129310744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A subpixel-based fingerprint reconstruction algorithm 一种基于子像素的指纹重建算法
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328951
Andreas Habegger, Lorenz Mueller, J. Goette, M. Jacomet
{"title":"A subpixel-based fingerprint reconstruction algorithm","authors":"Andreas Habegger, Lorenz Mueller, J. Goette, M. Jacomet","doi":"10.1109/NEWCAS.2012.6328951","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328951","url":null,"abstract":"The reconstruction of fingerprints from the output of sweep sensors is a crucial part of algorithms for fingerprint feature extraction. We present an efficient and accurate technique for fingerprint reconstruction from two-line sensors requiring sub-pixel methods. We propose a dedicated computation of the shift between two consecutive slices, yielding not only efficiency but also accuracy as we demonstrate by test data-sets.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132388807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis and optimization of noise response for low-noise CMOS image sensors 低噪声CMOS图像传感器噪声响应分析与优化
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329069
P. Martin-Gonthier, R. Molina, P. Cervantes, P. Magnan
{"title":"Analysis and optimization of noise response for low-noise CMOS image sensors","authors":"P. Martin-Gonthier, R. Molina, P. Cervantes, P. Magnan","doi":"10.1109/NEWCAS.2012.6329069","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329069","url":null,"abstract":"CMOS image sensors are nowadays widely used in imaging applications and particularly in low light flux applications. This is really possible thanks to a reduction of noise obtained, among others, by the use of pinned photodiode associated with a Correlated Double Sampling readout. It reveals new noise sources which become the major contributors. This paper presents noise measurements on low-noise CMOS image sensor. Image sensor noise is analyzed and optimization is done in order to reach an input referred noise of 1 electron rms by column gain amplifier insertion and dark current noise optimization. Pixel array noise histograms are analyzed to determine noise impact of dark current and column gain amplifier insertion. Transfer noise impact, due to the use of pinned photodiode (4T photodiode), is also measured and analyzed by a specific readout sequence.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129218221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system MTJ/ mos混合可变弹性VLSI系统的可扩展串行配置方案
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328965
M. Natsui, T. Hanyu
{"title":"Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system","authors":"M. Natsui, T. Hanyu","doi":"10.1109/NEWCAS.2012.6328965","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328965","url":null,"abstract":"A new circuit-characteristic configuration scheme of a nonvolatile logic circuit, where magnetic tunnel junction (MTJ) devices are combined with MOS transistors, is proposed for realizing process, voltage, temperature (PVT)-variation-aware VLSI systems. Faulty logic-function results due to PVT variation are detected by monitoring input-output characteristics of each logic-circuit cell, and adjusted by configuring resistance values of MTJ devices embedded into each logic-circuit cell. The resistance values of MTJ devices are programmed in bit-serial manner by the proposed scheme, which can suppress not only area overhead due to incorporating configuration function but also the number of control signals from peripheral circuitry. It results in adding the configuration capability with compact and scalable implementation.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115161964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An ultra-low power redundant split-DAC SA-ADC using power-optimized programmable comparator 一种超低功耗冗余分路dac SA-ADC，采用功率优化可编程比较器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329012
A. Arian, Saied Hosseini-Khayat
{"title":"An ultra-low power redundant split-DAC SA-ADC using power-optimized programmable comparator","authors":"A. Arian, Saied Hosseini-Khayat","doi":"10.1109/NEWCAS.2012.6329012","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329012","url":null,"abstract":"An ultra-low power successive approximation (SA) analog-to-digital converter (ADC) based on the redundant search algorithm is proposed. The power consumption of the comparator is significantly reduced through gain control of the preamplifier during conversion phase. The number of analog sampling switches is reduced to one by introducing modified clock boosting switch. A single-ended 8-bit SA-ADC is designed in a 0.18 μm CMOS process. Our simulation results show that at a supply voltage of 0.9 V and an output rate of 500 kS/s, the SA-ADC achieves a peak signal-to-noise-and-distortion (SNDR) ratio of 48 dB, and a power consumption of 1.63 μW, resulting in a figure of merit of 15.9 fJ/conversion-step.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"409 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124355413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Wideband mechanical energy harvester based on piezoelectric longitudinal mode 基于压电纵向模式的宽带机械能采集器
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329054
B. Seddik, G. Despesse, E. Defay
{"title":"Wideband mechanical energy harvester based on piezoelectric longitudinal mode","authors":"B. Seddik, G. Despesse, E. Defay","doi":"10.1109/NEWCAS.2012.6329054","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329054","url":null,"abstract":"This paper presents how an adjustable electrical load can be used to achieve a wideband mechanical vibration energy harvester based on piezoelectric material. We discuss within this paper the design optimization of the developed structure in terms of coupling mode and cantilever shape. The developed device is based on longitudinal piezoelectric mode; it features two principal modes, 208 Hz at short circuit condition and 294 Hz at open condition. The adjustable electrical load coupled with the piezoelectric material will allow a controllable shift of the resonant frequency between these two principal modes.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116367196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Neuro-SRAM technology Neuro-SRAM技术
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328963
N. Saleh, A. Haidar, A. Kassem, Lina A. Nimri
{"title":"Neuro-SRAM technology","authors":"N. Saleh, A. Haidar, A. Kassem, Lina A. Nimri","doi":"10.1109/NEWCAS.2012.6328963","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328963","url":null,"abstract":"A Neuro-SRAM design methodology composed of a set of basic SRAM cells is proposed, facilitating the identification of both the limiting mechanisms and the corrective design enhancements. Also, a neural decoder, which is the responsible for selecting these cells, is proposed and simulated.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121257009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high level mixed hardware/software modeling framework for rapid performance estimation 用于快速性能评估的高级混合硬件/软件建模框架
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6328999
Joffrey Kriegel, A. Pegatoquet, M. Auguin, Florian Broekaert
{"title":"A high level mixed hardware/software modeling framework for rapid performance estimation","authors":"Joffrey Kriegel, A. Pegatoquet, M. Auguin, Florian Broekaert","doi":"10.1109/NEWCAS.2012.6328999","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6328999","url":null,"abstract":"This paper presents a high level mixed hardware/-software modeling framework for rapid performance estimation. Our approach deals with both mono-processor and multi-threaded application for multi-core processors. Mechanisms such as parallelism and preemption are handled to simulate the correct behavior of the architecture. Obtained results show an error margin of less than 20% of estimation performance for several applications running on different hardware platforms.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121441367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Influence of the output harmonic networks of classes F and F−1 power amplifiers in LINC systems LINC系统中F类和F−1类功率放大器输出谐波网络的影响
10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI: 10.1109/NEWCAS.2012.6329060
Ronald Montesinos, C. Berland, Mazen Abi-Hussein, O. Venard, P. Descamps
{"title":"Influence of the output harmonic networks of classes F and F−1 power amplifiers in LINC systems","authors":"Ronald Montesinos, C. Berland, Mazen Abi-Hussein, O. Venard, P. Descamps","doi":"10.1109/NEWCAS.2012.6329060","DOIUrl":"https://doi.org/10.1109/NEWCAS.2012.6329060","url":null,"abstract":"This paper presents the influence of the harmonic networks of class F and inverse F power amplifiers (PAs) in the LINC (LInear amplification using Non-linear Components) transmitter architecture. The analysis and design of these classes with CHIREIX combiner are realised using Agilent ADS software. We use for this work a GaN HEMT transistor from Cree. Performances of the system are evaluated using a 16QAM modulation at 900MHz with 5.63dB Peak-to-Average Power Ratio (PAPR). This study shows the advantages and drawbacks of even/odd harmonics in drain curves of these PA classes as well as the tradeoff linearity-efficiency for the LINC architecture.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124975987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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