Optimize hardware with fixed-point variable length phase factors

Abstract

Fast Fourier Transforms (FFTs) are highly parallel in nature and consist of simple addition, subtraction, and complex rotation operators with phase factors (a.k.a. twiddle factors). With the advent of FPGAs and other reconfigurable seas-of-logic, it is now possible to construct a fully parallel FFT structure where the phase factors are now constants and good targets for hardware optimization. By varying the fixed-point length of the phase factors using phase angle error percentage as a control for the variable length phase factor quantizer, the number of shifted adders required to implement the complex rotation operators can be reduced. Performance comparisons of fixed length and variable length phase factors, along with two quantizer rounding modes, are investigated.