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Adaptive photovoltaic cell simulation with maximum power point tracking simulation for accurate energy predictions 自适应光伏电池仿真与最大功率点跟踪仿真，以实现准确的能量预测
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126721
C. Schuss, T. Rahkonen
{"title":"Adaptive photovoltaic cell simulation with maximum power point tracking simulation for accurate energy predictions","authors":"C. Schuss, T. Rahkonen","doi":"10.1109/NORCHP.2011.6126721","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126721","url":null,"abstract":"This paper presents a modelling tool for photovoltaic (PV) cells, which can build and optimise a simulation model based on measured data, and can plot the I-V (Current-Voltage) and the P-V (Power-Voltage) curve. Furthermore, it allows using solar irradiation and temperature profiles to make cumulative energy simulations during a day, for example, and compare the efficiency of different MPPT algorithms by simulating their behaviour and performance. It was found out that realistic temperature data is very crucial for estimating the effects of MPPT algorithms. The tool is implemented in LabVIEWTM, which makes it easy to combine with actual measurements and offers a suitable graphic user interface (GUI).","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131497735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Electrical properties of CVD-graphene FETs cvd -石墨烯fet的电学特性
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126720
Johanna Anteroinen, Wonjae Kim, K. Stadius, J. Riikonen, H. Lipsanen, J. Ryynänen
{"title":"Electrical properties of CVD-graphene FETs","authors":"Johanna Anteroinen, Wonjae Kim, K. Stadius, J. Riikonen, H. Lipsanen, J. Ryynänen","doi":"10.1109/NORCHP.2011.6126720","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126720","url":null,"abstract":"Graphene field-effect transistors (GFET) were first presented in 2004, and quickly became an interesting electronics research topic due to the many promises that the material holds. We have fabricated GFETs using an IC-compatible chemical vapour deposition (CVD) process. This paper presents experimental results of graphene field-effect transistors with CVD grown graphene layer. In addition, this paper reviews briefly the state-of-the-art GFETs and device physics.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Explorations of optimal core and cache placements for Chip Multiprocessor 探索最佳核心和缓存放置的芯片多处理器
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126728
T. Xu, P. Liljeberg, H. Tenhunen
{"title":"Explorations of optimal core and cache placements for Chip Multiprocessor","authors":"T. Xu, P. Liljeberg, H. Tenhunen","doi":"10.1109/NORCHP.2011.6126728","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126728","url":null,"abstract":"In this paper, we study and analyse optimal core and cache placements for modern Chip Multiprocessors (CMPs). As the number of cores increases, traditional on-chip interconnects such as bus and crossbar suffer from poor scalability and low efficiency. Ring based design has been proposed and implemented to mitigate these problems. However, the continuation growth of number of cores will render the ring interconnect infeasible. Network based designs are therefore proposed for future CMPs for better scalability. In this paper, we explore the interconnect of a state-of-the-art CMP. We analyse and compare the implementation of the ring-based and the network-based interconnect. The placement of cores and caches in a network is proved crucial for system performance. We investigate optimal core/cache placement for CMPs. The benchmark results are presented by using a cycle accurate full system simulator. Results show that, by using the optimal network interconnect, compared with the ring interconnect, the average network latency and execution time are reduced by 11.93% and 19.53% respectively, for four configurations and two applications.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133243405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 0.13µm CMOS ΔΣ PLL FM transmitter 0.13µm CMOS ΔΣ锁相环调频发射机
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126744
Ying Wu, Xiaodong Liu, D. Ye, Vijay Viswam, Lin Zhu, P. Lu, D. Radjen, H. Sjöland
{"title":"A 0.13µm CMOS ΔΣ PLL FM transmitter","authors":"Ying Wu, Xiaodong Liu, D. Ye, Vijay Viswam, Lin Zhu, P. Lu, D. Radjen, H. Sjöland","doi":"10.1109/NORCHP.2011.6126744","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126744","url":null,"abstract":"A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131703738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS 开关活动对65nm亚vt CMOS能量最小电压的影响
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126748
O. Andersson, S. M. Y. Sherazi, J. Rodrigues
{"title":"Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS","authors":"O. Andersson, S. M. Y. Sherazi, J. Rodrigues","doi":"10.1109/NORCHP.2011.6126748","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126748","url":null,"abstract":"This paper presents an analysis on energy dissipation of designs when operated in sub-threshold (sub-VT) regime. Four reference architectures are used to investigate the impact of switching activity μe on energy and energy minimum voltage (EMV). The designs are synthesized in a 65 nm low-leakage CMOS technology with high-threshold voltages cells. A sub-VT energy model is applied to characterize the designs in the sub-VT domain. The simulation results show that with low μe the EMV of a design moves closer to the threshold voltage and visa versa, up to a change of 104mV for the observed architectures. Furthermore a loss in frequency by one order of magnitude is observed. It is also observed that for these architectures operation at a sub-optimal frequency leads to loss in energy dissipation. However, by correct selection of operational clock frequency the energy dissipation is reduced by order of magnitudes.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116803144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems LTE系统中基数3和基数5 FFT内核的硬件实现
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126703
J. Löfgren, P. Nilsson
{"title":"On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems","authors":"J. Löfgren, P. Nilsson","doi":"10.1109/NORCHP.2011.6126703","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126703","url":null,"abstract":"This paper treats the hardware architecture and implementation of mixed radix FFTs with cores of radix 3 and radix 5 in addition to the standard radix 2 core. The implementation flow graphs of the higher radix cores are presented together with a description of how these cores affect a pipelined FFT implementation. It is shown that the mixed radix FFT is more expensive than the radix 2 implementation - a mixed radix FFT of 1200 points require 36 real multipliers in a pipelined implementation whereas a 2048 radix 2 FFT needs 30 real multipliers. However, half of the multipliers in the mixed radix case can be constant. Therefore it is still feasible to use the mixed radix FFT if an algorithm calls for it.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124141238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems 快于nyquist多载波系统中IOTA滤波器架构的复杂性分析
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126704
D. Dasalukunte, S. Mehmood, V. Öwall
{"title":"Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems","authors":"D. Dasalukunte, S. Mehmood, V. Öwall","doi":"10.1109/NORCHP.2011.6126704","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126704","url":null,"abstract":"This paper has evaluated the overhead requirements for IOTA pulse shaping filters employed in faster-than-Nyquist multicarrier systems. Faster-than-Nyquist signaling has shown the promise of improving bandwidth efficiency, but comes at the cost of increased processing complexity in the transceiver. The IOTA filter being one of the blocks contributing for the processing overhead, different architectural options have been evaluated. A comparison is drawn between the architectures of the IOTA filter and the suitable architecture with moderate hardware overhead is chosen for implementation.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121646678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Very high bandwidth semi-digital PLL with large operating frequency range 高带宽半数字锁相环，工作频率范围大
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126710
Vivekanandh Elangovan, M. Dietl, P. Sareen
{"title":"Very high bandwidth semi-digital PLL with large operating frequency range","authors":"Vivekanandh Elangovan, M. Dietl, P. Sareen","doi":"10.1109/NORCHP.2011.6126710","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126710","url":null,"abstract":"A new method of designing a very high bandwidth semi-digital PLL with a large operating frequency range from 100MHz to 1GHz is proposed. The PLL is modelled in Z-domain. The simulation results is also matched with the modelling to ensure that the PLL is stable for very high bandwidth. The bandwidth achieved is (1 over 4)th of the input reference frequency for the whole operating range mentioned.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123101141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOS 65纳米CMOS设计的两种宽带Balun-LNAs的比较和IIP2分析
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126716
Lin Zhu, Martin Liliebladh
{"title":"Comparison and IIP2 analysis of two wideband Balun-LNAs designed in 65nm CMOS","authors":"Lin Zhu, Martin Liliebladh","doi":"10.1109/NORCHP.2011.6126716","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126716","url":null,"abstract":"Two wideband Balun-LNA configurations have been designed in 65nm COMS technology. Both of them employ a single-to-differential (S-to-D) conversion topology composed of a common gate (CG) amplifying stage and a common source (CS) stage, providing output balancing and noise and distortion cancelling. One is inductorless and the other one exploits gain-boosting current-balancing topology. With 2.5V and 2.5V/1.8V supply the LNAs achieve voltage gains of 24.5dB and 22.8dB, noise figures of below or close to 3dB, input second-order intercept points (IIP2) of 31dB and 41.8dB, respectively. In addition, the sensitivity of IIP2 is deeply investigated.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"65 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129544551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Computational and implementation complexity of polynomial evaluation schemes 多项式评估方案的计算和实现复杂性
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126735
Muhammad Abbas, O. Gustafsson
{"title":"Computational and implementation complexity of polynomial evaluation schemes","authors":"Muhammad Abbas, O. Gustafsson","doi":"10.1109/NORCHP.2011.6126735","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126735","url":null,"abstract":"In this work, we consider the computational complexity of different polynomial evaluation schemes. By considering the number of operations of different types, critical path, pipelining complexity, and latency after pipelining, high-level comparisons are obtained. These can then be used to short list suitable candidates for an implementation given the specifications. Not only multiplications are considered, but they are divided into data-data multiplications, squarers, and data-coefficient multiplications, as the latter can be optimized depending on implementation architecture and application.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"178 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132242941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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