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Yield modeling and yield-aware mapping for application specific networks-on-chip 针对特定应用的片上网络的产量建模和产量感知映射
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126733
Seyyed Hassan Khalilinezhad, A. Reza, M. Reshadi
{"title":"Yield modeling and yield-aware mapping for application specific networks-on-chip","authors":"Seyyed Hassan Khalilinezhad, A. Reza, M. Reshadi","doi":"10.1109/NORCHP.2011.6126733","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126733","url":null,"abstract":"Network-on-chip has been proposed as an interconnection solution for increasing number of cores on chips. Increasing number of cores affects the yield of the devices and systems that make use of the multi core chips. Two major factors that affect the system yield are routers and links yield. We propose a yield model which uses variable router yield for the system. Based on this model, a yield aware mapping is proposed. Our proposed mapping algorithm improves yield up to 30 percent. Although the algorithm has decreased power consumption up to 15 percent, it has caused delay to increase 39 percent.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123118302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An adaptive router architecture for heterogeneous 3D Networks-on-Chip 一种异构3D片上网络的自适应路由器架构
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126725
Michael Opoku Agyeman, A. Ahmadinia
{"title":"An adaptive router architecture for heterogeneous 3D Networks-on-Chip","authors":"Michael Opoku Agyeman, A. Ahmadinia","doi":"10.1109/NORCHP.2011.6126725","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126725","url":null,"abstract":"Three dimensional Network-on-Chip (3D NoC) is becoming increasingly popular to address the on-chip communication demands of modern multi-core systems. However, architectural framework of the 3D router uses more buffer resources than conventional 2D routers. Also, homogeneous 3D NoC topologies have more TSVs which have a costly and complex manufacturing process. To improve the performance and manufacturing cost in 3D NoCs we propose adaptive router architectures for heterogeneous and homogeneous 3D NoCs which combine both the area and performance benefits of static 2D and 3D router architectures. Experimental results show that with a negligible penalty of up to 0.4% in maximum operating frequency, we achieved performance improvement of up to 34% by replacing 2D static routers with adaptive routers in heterogeneous architectures.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128588163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A divide-by-three regenerative frequency divider using a subharmonic mixer 使用次谐波混频器的三倍再生分频器
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126726
B. Jackson, C. Saavedra
{"title":"A divide-by-three regenerative frequency divider using a subharmonic mixer","authors":"B. Jackson, C. Saavedra","doi":"10.1109/NORCHP.2011.6126726","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126726","url":null,"abstract":"A regenerative frequency divider topology is used with a ×2 subharmonic mixer to realize a divide-by-three frequency divider. The circuit accepts input signals in the range of 5.2 GHz to 5.5 GHz and produces signals from 1.73 GHz to 1.83 GHz. Measured results show a maximum conversion gain of 0 dB and at least a 30 dB suppression of all undesired harmonic components at the output. The circuit core consumes 44 mW of dc power and ideas are provided on how to reduce the power draw. The chip was fabricated on a standard 0.13-µm CMOS process and it occupies an area of 1.0 mm2 including bonding pads.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130557974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On wafer X-parameter based modeling of a switching cascode power amplifier 基于晶圆x参数的开关级联码功率放大器建模
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126705
Yelin Wang, D. Sira, T. Nielsen, O. K. Jensen, T. Larsen
{"title":"On wafer X-parameter based modeling of a switching cascode power amplifier","authors":"Yelin Wang, D. Sira, T. Nielsen, O. K. Jensen, T. Larsen","doi":"10.1109/NORCHP.2011.6126705","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126705","url":null,"abstract":"X-parameters have been introduced as the natural extension of S-parameters capable of characterizing a nonlinear device excited by a large-signal input. This paper describes validation of the X-parameter model of a switching cascode power amplifier (PA), which has strong nonlinearity. The X-parameter model of the PA was measured and extracted by an Agilent N5245A PNA-X. Measurements were done on wafer and deem-bedded to the input and output pads of the device. An Enhanced Data rates for GSM Evolution (EDGE) signal was applied to the model for simulations. The simulated relative levels of output spectrum and RMS value of error vector magnitude (EVM) were compared with the measured data in order to validate the X-parameter model. A good match was achieved between the simulation and measurement. The maximum difference between the simulated and measured relative levels of output spectrum is 4 dB. The maximum error between the simulated and measured EVM is less than 3 %-point.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126794698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Highly linear direct conversion receiver using customized on-chip balun 高度线性直接转换接收器使用定制的片上平衡
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126739
Xiaodong Liu, Vijay Viswam, S. Andersson, J. Wernehag, I. Din, P. Andreani
{"title":"Highly linear direct conversion receiver using customized on-chip balun","authors":"Xiaodong Liu, Vijay Viswam, S. Andersson, J. Wernehag, I. Din, P. Andreani","doi":"10.1109/NORCHP.2011.6126739","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126739","url":null,"abstract":"This paper presents a highly linear radio frequency receiver front-end with on-chip balun for cellular application at 2GHz in 65nm CMOS technology. Based on direct conversion architecture, the implemented front-end comprises a customized on-chip balun for single-ended to differential signal conversion, a differential common-gate low noise amplifier and voltage mode quadrature passive mixer. The simulated in-band compression point is −0.5dBm and third order input intercept point is +6.2dBm. An out-of-band blocker compression point up to +4.8dBm and third order input intercept point of +16dBm are achieved thanks to the frequency translation filtering technique. The low-noise amplifier consumes 3mA current using 1.8V supply. The overall noise figure including balun loss, low-noise amplifier, mixer and a simplified model of a baseband filter is 3.8dB.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134279018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel low-energy match line sensing scheme for ternary content addressable memory using charge sharing 基于电荷共享的三元内容可寻址存储器低能量匹配线传感方案
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126747
Syed Iftekhar Ali, M. Islam
{"title":"A novel low-energy match line sensing scheme for ternary content addressable memory using charge sharing","authors":"Syed Iftekhar Ali, M. Islam","doi":"10.1109/NORCHP.2011.6126747","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126747","url":null,"abstract":"A new match line sensing scheme for ternary content addressable memory (TCAM) is presented in this paper. Selective precharge is combined with charge sharing technique to reduce the match line (ML) energy consumption. Simulation performed using 130nm 1.2V CMOS logic shows minimum ∼35% dynamic energy reduction compared to current race (CR) scheme. The technique also achieves ∼41% speed improvement. Unlike many existing schemes, the proposed scheme uses minimum number of control signals which need to be generated off-chip. Also, there is no analog control signal requiring manual tuning as has been used in CR or many CR-like schemes.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127321249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches 单端低噪声多频带LNA与可编程集成匹配和高隔离开关
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126737
Tobias Tired, P. Andreani
{"title":"Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches","authors":"Tobias Tired, P. Andreani","doi":"10.1109/NORCHP.2011.6126737","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126737","url":null,"abstract":"This paper describes a novel 90nm single-ended multiband input LNA preceded by RF input switches connected to an on-chip balun intended to drive a differential mixer. The architecture achieves a low noise figure of 1.8dB. The advantage with the proposed architecture is that it is fully single-ended with on-chip programmable narrow-band matching eliminating the need of off-chip components. Especially in multiband integrated radios a single-ended LNA is highly desirable since the pin-count for the LNAs is reduced by half compared with a differential architecture. The PCB routing of the RF input signal is simplified. Narrow-band matching is advantageous compared to common broadband matching since this adds attenuation of out of band interferers and suppresses conversion of 3rd LO harmonic. This is important for the coexistence of cellular systems with e.g. WLAN 802.11a operating in the 5GHz band.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"276 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113990965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs 在fpga上实现窄带频率响应掩蔽的高效窄过渡带FIR滤波器
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126702
Syed Asad Alam, O. Gustafsson
{"title":"Implementation of narrow-band frequency-response masking for efficient narrow transition band FIR filters on FPGAs","authors":"Syed Asad Alam, O. Gustafsson","doi":"10.1109/NORCHP.2011.6126702","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126702","url":null,"abstract":"The complexity of narrow transition band FIR filters is high and can be reduced by using frequency response masking (FRM) techniques. These techniques use a combination of periodic model filters and masking filters. In this paper, we show that time-multiplexed FRM filters achieve lower complexity, not only in terms of multipliers, but also logic elements compared to time-multiplexed single stage filters. The reduced complexity also leads to a lower power consumption. Furthermore, we show that the optimal period of the model filter is dependent on the time-multiplexing factor.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"459 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134004982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A mixed mode design flow for multi GHz ADPLLs 多GHz adpll的混合模式设计流程
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126714
Muhammad Shakir, Mohammed Abdulaziz, P. Lu, P. Andreani
{"title":"A mixed mode design flow for multi GHz ADPLLs","authors":"Muhammad Shakir, Mohammed Abdulaziz, P. Lu, P. Andreani","doi":"10.1109/NORCHP.2011.6126714","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126714","url":null,"abstract":"A systematic design approach for All Digital Phase Locked Loops (ADPLL) is presented. The whole system excluding Digitally Controlled Oscillator (DCO) and the Time to Digital Converter (TDC) can be synthesized easily in digital design flow. By using standard digital cells, no custom digital cells are needed. All the key problems in synthesis are solved well. The ADPLL is implemented in 90-nm CMOS process technology with the divider-by-two output clock of 2.7GHz. The current consumption is 6.5mA under the power supply of 1.2V.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115850515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Square topology: A novel topology for NoCs 方形拓扑:noc的一种新颖拓扑
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126731
Hossein Doroud, M. Ghorbanian, R. Sabbaghi‐Nadooshan
{"title":"Square topology: A novel topology for NoCs","authors":"Hossein Doroud, M. Ghorbanian, R. Sabbaghi‐Nadooshan","doi":"10.1109/NORCHP.2011.6126731","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126731","url":null,"abstract":"This paper proposes square topology as an efficient topology for Network-on-Chips (NoCs). Although the proposed topology imposes the cost near to that of the mesh topology, the proposed topology 1) provides lower diameter for NoC, 2) offers better performance under uniform and hotspot traffic pattern. In our simulation, the proposed square topology had better performance in comparison to other topologies specifically meshes and spidergon topology.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129802507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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