Ying Wu, Xiaodong Liu, D. Ye, Vijay Viswam, Lin Zhu, P. Lu, D. Radjen, H. Sjöland
{"title":"A 0.13µm CMOS ΔΣ PLL FM transmitter","authors":"Ying Wu, Xiaodong Liu, D. Ye, Vijay Viswam, Lin Zhu, P. Lu, D. Radjen, H. Sjöland","doi":"10.1109/NORCHP.2011.6126744","DOIUrl":null,"url":null,"abstract":"A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"78 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 NORCHIP","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NORCHP.2011.6126744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A short range FM transmitter is presented. It uses an architecture where the output frequency of a phase locked loop (PLL) is modulated by varying the division number of the feedback divider, using the 1-bit output of a ΔΣ ADC. The measured total harmonic distortion (THD) plus noise is less than 1% at 75 kHz deviation. The transmitter is fully integrated in a 0.13µm CMOS process and the core area is 0.24 mm2. The current consumption is 4.4mA from a 1.2V supply.