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Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process corner 使用校准的基准电压来提高开关电容σ - δ adc的性能
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126717
R. Spilka, D. Gruber, T. Ostermann
{"title":"Use of a calibrated voltage reference to enhance the performance of switched capacitor sigma-delta ADCs over process corner","authors":"R. Spilka, D. Gruber, T. Ostermann","doi":"10.1109/NORCHP.2011.6126717","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126717","url":null,"abstract":"To enhance the performance of a switched-capacitor sigma-delta ADC we present a digitally trimmable on-chip voltage reference with a minimum step size in the range of 1–2mV@1.5–2.5V. Due to a multi-stage calibration scheme the output voltage of the reference could be additionally adjusted over a wide range of 500–700mV@1.7–2.1V. This can be useful to later adjust the reference levels in the sigma-delta modulator after design time (post-production).","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123527117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Architecture-level analysis and evaluation of transient errors on NoC NoC暂态误差的体系结构级分析与评估
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126730
Jiajia Jiao, Yuzhuo Fu, Jiang Jiang
{"title":"Architecture-level analysis and evaluation of transient errors on NoC","authors":"Jiajia Jiao, Yuzhuo Fu, Jiang Jiang","doi":"10.1109/NORCHP.2011.6126730","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126730","url":null,"abstract":"Scaling IC technology, lower voltage supply and high frequency etc cause transient errors to dominate in VLSI reliability design. NoC, as the most promising communication infrastructure for many-core system, also faces bits upset challenge due to transient errors. In this paper, we focus on analysis and evaluation of transient errors on NoC from architecture perspective: 1) classify the transient errors in NoC and analyse the cross-relationship between different types of errors to explore fine grain transient errors effect; 2) define the unified architecture-level metrics for evaluating transient errors effect on performance and reliability to guide fault tolerance methods selection; 3) do some cases study about transient errors in NoC based on accurate simulation results to validate our approach.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127930517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A GALS ASIC implementation from a CAL dataflow description 基于CAL数据流描述的GALS ASIC实现
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126740
H. Prabhu, Sherine Thomas, J. Rodrigues, T. Olsson, A. Carlsson
{"title":"A GALS ASIC implementation from a CAL dataflow description","authors":"H. Prabhu, Sherine Thomas, J. Rodrigues, T. Olsson, A. Carlsson","doi":"10.1109/NORCHP.2011.6126740","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126740","url":null,"abstract":"This paper presents low power hardware generation, based on a CAL actor language dataflow implementation. The CAL language gives a higher level of abstraction and generate both hardware and software description. The original CAL flow is targeted for hardware-software co-design of complex systems on FPGA. Modifications are done to the original CAL flow to facilitate low power ASIC implementations. The hardware-software co-design and Globally Asynchronous Locally Synchronous (GALS) design at a higher level of abstraction provides more freedom for design-space exploration and reduced design time. Performance is evaluated by a reference design, Orthogonal Frequency-Division Multiplexing (OFDM) multi-standard channel estimator based on robust Minimum Mean-Square Error (MMSE) algorithm. Higher throughput is attained due to inherent parallelism in CAL dataflow and reduced design time for GALS implementation.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"75 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120926522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS 一个频率分辨率为625Hz的2.7GHz无分频全数字锁相环，采用90nm CMOS
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126743
Mohammed Abdulaziz, Muhammad Shakir, P. Lu, P. Andreani
{"title":"A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS","authors":"Mohammed Abdulaziz, Muhammad Shakir, P. Lu, P. Andreani","doi":"10.1109/NORCHP.2011.6126743","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126743","url":null,"abstract":"A divider-less all digital phase locked loop (ADPLL) with a high frequency resolution is implemented. All blocks excluding digitally controlled oscillator (DCO) and time to digital converter (TDC) are realized in standard digital design which consumes less power. The DCO core adopts an improved source-varactor LC resonant tank to achieve a 20KHz frequency resolution. With the help of an additional ΔΣ modulator, the final frequency resolution is 625Hz. This work is simulated in 90nm CMOS process technology and consumes 7.6mW (DCO occupies 97.4%) under the power supply of 1.2V.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115332668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power programmable frequency divider for IEEE 802.15.4a standard 低功耗可编程分频器，符合IEEE 802.15.a标准
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126749
D. Martynenko, G. Fischer, O. Klymenko
{"title":"Low power programmable frequency divider for IEEE 802.15.4a standard","authors":"D. Martynenko, G. Fischer, O. Klymenko","doi":"10.1109/NORCHP.2011.6126749","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126749","url":null,"abstract":"This paper presents a frequency divider with a programmable division ratio between 208 and 320 intended for the standard IEEE 802.15.4a. The divider is based on high speed, low power, triple modulus prescalers. The wide division range is achieved by cascading these programmable prescalers. Each prescaler includes a phase selector and an ECL D-flip-flop which acts as a divider by 2. The triple operation of the prescaler is achieved by switching between different output phases of the D-flip-flop in the positive direction from 0° to 270° and to the negative direction from 270° to 0°. In addition, a clock of 499.2 MHz with 50% duty cycle is available independent of the selected communication channel. The proposed divider has been evaluated for a SiGe BiCMOS technology and a maximum simulated input frequency of at least 13.5 GHz has been achieved.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115850573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
IR-UWB technology on next generation RFID systems 下一代射频识别系统的超宽带技术
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126697
K. Lee, H. A. Hjortland, T. Lande
{"title":"IR-UWB technology on next generation RFID systems","authors":"K. Lee, H. A. Hjortland, T. Lande","doi":"10.1109/NORCHP.2011.6126697","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126697","url":null,"abstract":"Radio-frequency identification (RFID) systems are widely used in our daily life. Although several proposed solutions are in production, limitations are still significant. In this paper, the current RFID technology is reviewed and major shortcomings are discussed. Our expected features on next generation RFID systems are described. Finally, we propose an impulse-radio (IR) ultra-wideband (UWB) RFID system and present how to improve the performance by using IR-UWB technology.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128475875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Magnitude scaling for increased SFDR in DDFS DDFS中SFDR增加的幅度缩放
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126708
P. Kallstrom, O. Gustafsson
{"title":"Magnitude scaling for increased SFDR in DDFS","authors":"P. Kallstrom, O. Gustafsson","doi":"10.1109/NORCHP.2011.6126708","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126708","url":null,"abstract":"When generating a sine table to be used in, e.g., frequency synthesis circuits, a widely used way to assign the table content is to simply take a sine wave with the desired amplitude and quantize it using rounding. This results in uncontrolled rounding of up to 0.5 LSB, causing some noise. In this paper we present a method for increasing the signal quality, simply by adjust the amplitude within a ±0.5 range from the intended. This will not affect the maximum value of the sinusoid, but can increase the spurious free dynamic range with some dB.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127609049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Dynamic bias schemes for class-C VCOs c类压控振荡器的动态偏置方案
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126718
Luca Fanori, P. Andreani
{"title":"Dynamic bias schemes for class-C VCOs","authors":"Luca Fanori, P. Andreani","doi":"10.1109/NORCHP.2011.6126718","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126718","url":null,"abstract":"In class-C VCOs the trade-off between oscillation amplitude and start-up condition reduces the advantages of this topology with the respect to the traditional class-B operation. In this paper a dynamic bias scheme able to break this ultimate trade-off is presented. Two different topologies are reported. The first VCO uses an active current tail generator, while the second VCO has a passive resistive tail. Both solutions, simulated in a CMOS 65nm process, oscillate at 7.2GHz and show a phase noise of −126dBc/Hz @ 1MHz while drawing 11mA from a 1.2V supply voltage, resulting in a figure-of-merit of −191dBc/Hz.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127733665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Highly reliable and power efficient NOC interconnects 高度可靠和节能的NOC互连
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126732
Deena M. Zamzam, Mohamed A. Abd El-Ghany, K. Hofmann, M. Ismail
{"title":"Highly reliable and power efficient NOC interconnects","authors":"Deena M. Zamzam, Mohamed A. Abd El-Ghany, K. Hofmann, M. Ismail","doi":"10.1109/NORCHP.2011.6126732","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126732","url":null,"abstract":"Network on chip (NOC) architecture interconnects consume significant amount of power, have a large propagation delay and are susceptible to error due to deep sub-micron (DSM) noise. Major challenge that NOC design expected to face is related to intrinsic reliability. By incorporating error control coding schemes along the NOC interconnects, NOC architectures are able to provide correct functionality in the presence of different transient noise source. In this paper we present a novel coding scheme that increase the reliability of the NOC where the area is reduced by 19% and the consumed power by NOC interconnects is decreased by 51%. Butterfly fat tree architecture consumes the minimum power as compared to other NOC architectures.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120967066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS 65纳米CMOS中四态电流模式模拟通道解码器的晶体管尺寸
2011 NORCHIP Pub Date : 2011-11-01 DOI: 10.1109/NORCHP.2011.6126698
Reza Meraji, John B. Anderson, H. Sjöland, V. Öwall
{"title":"Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS","authors":"Reza Meraji, John B. Anderson, H. Sjöland, V. Öwall","doi":"10.1109/NORCHP.2011.6126698","DOIUrl":"https://doi.org/10.1109/NORCHP.2011.6126698","url":null,"abstract":"Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0µm/0.6µm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology.","PeriodicalId":108291,"journal":{"name":"2011 NORCHIP","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116244585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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