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Soft, curvilinear semiconductor devices for bio-integrated electronics 用于生物集成电子学的软曲线半导体器件
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994485
J. Rogers
{"title":"Soft, curvilinear semiconductor devices for bio-integrated electronics","authors":"J. Rogers","doi":"10.1109/DRC.2011.5994485","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994485","url":null,"abstract":"Biology is curved, soft and elastic; silicon wafers are not. Semiconductor technologies that can bridge this gap in form and mechanics will create new opportunities in devices that require intimate integration with the human body. This talk describes the development of ideas for electronics that offer the performance of state-of-the-art, wafer-based systems but with the mechanical properties of a rubber band. We explain the underlying materials science and mechanics of these approaches, and illustrate their use in bio-integrated, ‘tissue-like’ electronics with unique capabilities in electrocorticography and cardiac electrophysiology, in both endocardial and epicardial modes. In vivo demonstrations with animal models illustrate the functionality offered by these technologies, and suggest several clinically relevant applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126121403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A hybrid ferroelectric and charge nonvolatile memory 一种混合铁电和电荷非易失性存储器
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994474
S. Rajwade, K. Auluck, J. Shaw, K. Lyon, E. Kan
{"title":"A hybrid ferroelectric and charge nonvolatile memory","authors":"S. Rajwade, K. Auluck, J. Shaw, K. Lyon, E. Kan","doi":"10.1109/DRC.2011.5994474","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994474","url":null,"abstract":"We introduce a new nonvolatile memory that incorporates ferroelectric (FE) switching layer and charge-storage floating node in a single gate stack. This hybrid FE-charge design reduces the depolarization field in the FE layer as well as increases the memory window over conventional FE-FET. The magnitude of the electric field in the tunnel dielectric is reduced at retention and enhanced at program/erase from the FE polarization. This paper discusses the working principle, gate stack design, fabrication and experimental results of this hybrid design compared to FE-FET and charge-trap Flash.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129105254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The effect of field effect device channel dimensions on the effective mobility of graphene 场效应器件沟道尺寸对石墨烯有效迁移率的影响
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994424
A. Venugopal, J. Chan, W. Kirk, L. Colombo, E. Vogel
{"title":"The effect of field effect device channel dimensions on the effective mobility of graphene","authors":"A. Venugopal, J. Chan, W. Kirk, L. Colombo, E. Vogel","doi":"10.1109/DRC.2011.5994424","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994424","url":null,"abstract":"Graphene is a possible candidate for post CMOS applications and mobility is a material characteristic that has been utilized to gauge the quality of the material[1]. Mobility of exfoliated graphene transferred on SiO2 has been reported to range from 2,000 to 25,000 cm2/V·s [1, 2]. The large variation is typically attributed to factors such as scattering by defects in the underlying substrate, residue from processing, charged impurity scattering and phonon scattering [3]. In most previous studies one of the primary assumptions made is that the mobility is independent of channel dimensions. In this study, we performed room temperature effective mobility measurements as a function of channel dimensions. The mobility exhibits clear channel length (Lch) and width (Wch) dependence and varies from less than 1,000 cm2/V·s to 7,000 cm2/V·s. Theoretical analysis of the conductivity (σ) in graphene devices as a function of Wch performed by Vasko et al [4]. is in agreement with our experimental results. Mobility values for back gated devices with well defined channel dimensions in literature [5] are seen to be consistent with the trend that we report here.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125593052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier 隧道-场效应晶体管结构，由于隧道势垒的栅极调制增强而提高了性能
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994440
L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, A. Ionescu
{"title":"Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier","authors":"L. De Michielis, L. Lattanzio, P. Palestri, L. Selmi, A. Ionescu","doi":"10.1109/DRC.2011.5994440","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994440","url":null,"abstract":"The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133397134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
Investigation on superlattice heterostructures for steep-slope nanowire FETs 陡坡纳米线场效应管的超晶格异质结构研究
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994497
E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani
{"title":"Investigation on superlattice heterostructures for steep-slope nanowire FETs","authors":"E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani","doi":"10.1109/DRC.2011.5994497","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994497","url":null,"abstract":"In this work we investigate the feasibility of a steep-slope nanowire FET based on the filtering of the high-energy electrons via a superlattice heterostructure in the source extension. Several material pairs are investigated for the superlattice, with the aim to identify the most promising ones with respect to the typical FET evaluation metrics. We found that the GaN-AlGaN pair provides excellent results, which led us to optimize its device structure. We obtain a peak SS ≈ 15 mV/dec and an ON-current approaching 1mA/μm.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133764730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High-resolution temperature sensing with source-gated transistors 采用源门控晶体管的高分辨率温度传感
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994463
R. Sporea, J. Shannon, S. Silva
{"title":"High-resolution temperature sensing with source-gated transistors","authors":"R. Sporea, J. Shannon, S. Silva","doi":"10.1109/DRC.2011.5994463","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994463","url":null,"abstract":"Source-gated transistors (SGTs) [1] are three-terminal devices in which the current is controlled by a potential barrier at the source. The gate voltage is used primarily to modulate the effective height of the source barrier. These devices have a number of operational advantages over conventional field-effect transistors, including a potentially much smaller saturation voltage and very low output conductance in saturation, which lead to low power operation and high intrinsic gain [2].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131909448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Effect of optical phonon scattering on the performance limits of ultrafast GaN transistors 光学声子散射对超高速GaN晶体管性能极限的影响
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994529
T. Fang, Ronghua Wang, Guowang Li, H. Xing, S. Rajan, D. Jena
{"title":"Effect of optical phonon scattering on the performance limits of ultrafast GaN transistors","authors":"T. Fang, Ronghua Wang, Guowang Li, H. Xing, S. Rajan, D. Jena","doi":"10.1109/DRC.2011.5994529","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994529","url":null,"abstract":"As GaN HEMTs are scaled down to push performance into 100's of GHz range, it is timely to investigate their performance limits. Unlike Si MOSFETs and most other III–V semiconductor based HEMTs, the electron - polar optical phonon interaction is exceptionally strong in GaN. As a result, the mean free path of hot electrons in GaN is λop ∼ 3.5nm, far shorter than typical HEMT gate lengths (Lg). Thus while Si MOSFETs and other III-V HEMTs can approach near ballistic behavior by reduction of parasitic delays and Lg, the situation is starkly different for GaN HEMTs. Here, we investigate the intrinsic performance limits of GaN HEMTs by incorporating the effect of polar optical phonon backscattering into a quasi-ballistic model. Then, we include parasitic elements and quantitatively investigate the degradation in performance. The method used is semi-analytical, and will prove very helpful in designing future generations of devices. The work not only sets a roadmap for scaling to high speeds, it also offers clear physical reasons for a number of unexplained features observed in state-of-the-art GaN HEMTs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130995477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor 自对准栅纳米柱In0.53Ga0.47As垂直隧道晶体管
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994498
D. Mohata, R. Bijesh, V. Saripalli, T. Mayer, S. Datta
{"title":"Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor","authors":"D. Mohata, R. Bijesh, V. Saripalli, T. Mayer, S. Datta","doi":"10.1109/DRC.2011.5994498","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994498","url":null,"abstract":"Tunnel field effect transistors (TFET) have gained interest recently owing to their potential in achieving sub-kT/q steep switching slope, thus promising low Vcc operation[1–5]. Steep switching slope has already been demonstrated in Silicon TFET [2]. However, it has been theoretically shown and experimentally proved that Si or SixGe1−x based homo-junction or hetero-junction TFETs would not meet the drive current requirement for future low power high performance logic applications [3]. III–V based hetero-junction TFETs have shown promise to provide MOSFET like high drive currents at low operating Vcc while providing the sub-kT/q steep switching slope[1,4,5]. However, the device design demands extremely scaled EOT and ultra-thin body double-gate geometry in order to achieve the desired transistor performance [4]. In this paper, we discuss a vertical TFET fabrication process with self-aligned gate [6] which can ultimately lead to the ultra-thin double-gate device geometry in order to achieve the desired TFET performance.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"313 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114959543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Tunnel FET-based pass-transistor logic for ultra-low-power applications 超低功耗应用的隧道场效应晶体管通管逻辑
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994452
Sung Hwan Kim, Z. Jacobson, P. Patel, C. Hu, T. Liu
{"title":"Tunnel FET-based pass-transistor logic for ultra-low-power applications","authors":"Sung Hwan Kim, Z. Jacobson, P. Patel, C. Hu, T. Liu","doi":"10.1109/DRC.2011.5994452","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994452","url":null,"abstract":"Germanium-source tunnel-FET-based pass-transistor logic gates are proposed and benchmarked against conventional CMOS logic gates via mixed-mode simulations, for 15 nm LG. For low throughput applications (>100 ps gate delay), TPTL is advantageous for reductions in dynamic energy and leakage power.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121585392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Top-gated single-electron transistor in germanium nanowires 锗纳米线顶门控单电子晶体管
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994425
Sung-Kwon Shin, Shaoyun Huang, N. Fukata, K. Ishibashi
{"title":"Top-gated single-electron transistor in germanium nanowires","authors":"Sung-Kwon Shin, Shaoyun Huang, N. Fukata, K. Ishibashi","doi":"10.1109/DRC.2011.5994425","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994425","url":null,"abstract":"Germanium nanowires (GeNWs) of the group IV semiconductors could be one of the attractive candidates for electron-spin based quantum devices because of their long electron-spin coherence time. Besides, Ge has an advantage over Si in terms of the larger quantum effects due to the smaller effective mass. Single-electron transistors (SETs) are basic building blocks of such devices. To define the spin configuration in the dot, it is necessary to reach a few-electron regime or an even-odd regime where the single spin is realized for the odd number of electrons in the dot. So far, we have developed processes to fabricate SETs using n-type monocrystalline GeNWs with a back gate, and succeeded in observing the even-odd effect [1]. In this work, we have developed fabrication processes of the top-gate SETs to enhance the gating efficiency, and succeeded in reaching a few-electron regime.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126782730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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