69th Device Research Conference最新文献_第9页

Observation of trap-assisted steep sub-threshold swing in schottky source/drain Al2O3/InAlN/GaN MISHEMT 捕集阱辅助下肖特基源/漏Al2O3/InAlN/GaN MISHEMT陡亚阈值摆动的观察

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994417

Qi Zhou, Hongwei Chen, Chunhua Zhou, Zhihong Feng, S. Cai, K. J. Chen

{"title":"Observation of trap-assisted steep sub-threshold swing in schottky source/drain Al2O3/InAlN/GaN MISHEMT","authors":"Qi Zhou, Hongwei Chen, Chunhua Zhou, Zhihong Feng, S. Cai, K. J. Chen","doi":"10.1109/DRC.2011.5994417","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994417","url":null,"abstract":"Devices with steep subthreshold swing (SS) are of great interest and significance in view of increasing subthreshold leakage current with the continuous MOSFET scaling. The standby power dissipation has grown due to the nonscalability of the SS to below 60 mV/dec at room temperature (RT). To circumvent this obstacle, novel devices that employ various turn-on mechanisms have been proposed1–4. In this work, we report the observation of steep SS∼20 mV/dec in Schottky source/drain (SSD) Al2O3/InAlN/GaN MIS-HEMTs over a drain bias range of 0.1 to 5 V. The devices also feature high ION/IOFF ratio (∼109) and appreciable current drive of IDmax=230 mA/mm at room temperature. The devices are also characterized at elevated temperature (T) up to 155 °C. Steep SS lower than the theoretical diffusion limit is consistently observed over the testing temperature range. It is suggested that the steep switching behavior is obtained through the means of a dynamic de-trapping process at the Al2O3/InAlN interface. The dynamic de-trapping enables a dynamic negative shift in the threshold voltage during the gate upswing and effectively facilitates the formation of a sub-threshold swing as steep as 18 mV/dec.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123805987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Barrier height, interface charge & tunneling effective mass in ALD Al2O3/AlN/GaN HEMTs ALD Al2O3/AlN/GaN hemt的势垒高度、界面电荷与隧穿有效质量

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994445

S. Ganguly, J. Verma, Guowang Li, T. Zimmermann, H. Xing, D. Jena

引用次数: 4

First AlN/GaN HEMTs power measurement at 18 GHz on Silicon substrate 首次在硅衬底上测量18ghz的AlN/GaN HEMTs功率

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994506

F. Medjdoub, M. Zegaoui, D. Ducatteau, N. Rolland, P. Rolland

{"title":"First AlN/GaN HEMTs power measurement at 18 GHz on Silicon substrate","authors":"F. Medjdoub, M. Zegaoui, D. Ducatteau, N. Rolland, P. Rolland","doi":"10.1109/DRC.2011.5994506","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994506","url":null,"abstract":"AlN/GaN heterostructure is an ideal candidate to push the limits of microwave GaN-based devices owing to the maximum theoretical spontaneous and piezoelectric difference between the epitaxial AlN barrier and the underlying GaN layer. If the tricky growth conditions of this binary can be controlled, AlN/GaN HEMTs promise breakthrough performances, superior to any other III-V nitride-based heterostructure [1]. In particular, this structure should allow the extension of the GaN-based frequency operation due to the possibility to significantly reduce the gate length while maintaining an appropriate gate-to-channel aspect ratio to mitigate short channel effects. However, gate leakage current remains a serious issue with such ultrathin barrier heterostructure and gate dielectrics that often leads to device instability are generally used to overcome this problem. Furthermore, there is an increasing interest in the growth of GaN-on-Si substrates because of its low cost, large size, good thermal conductivity and the potential for integration with Si-based devices. In this work, we developed a novel AlN/GaN HEMT technology on Si substrate. The highest GaN-on-Si drain current density as well as a record transconductance together with excellent RF performance have been achieved. Additionally, AlN/GaN HEMT power measurements at 18 GHz have been performed for the first time. These results show the outstanding potential of this structure to extend GaN-on-Si performances to millimeter wave applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129931935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994531

N. Nidhi, S. Dasgupta, J. Lu, F. Wu, S. Keller, J. Speck, U. Mishra

引用次数: 3

Combinational and sequential logic with transistors based on individual carbon nanotubes 基于单个碳纳米管的晶体管组合和顺序逻辑

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994477

H. Ryu, D. Kalblein, U. Zschieschang, O. Schmidt, H. Klauk

{"title":"Combinational and sequential logic with transistors based on individual carbon nanotubes","authors":"H. Ryu, D. Kalblein, U. Zschieschang, O. Schmidt, H. Klauk","doi":"10.1109/DRC.2011.5994477","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994477","url":null,"abstract":"Field-effect transistors (FETs) that utilize an individual semiconducting carbon nanotube (CNT) as the channel are potentially useful for the realization of logic circuits with high integration densities that can be fabricated on transparent, large-area substrates, such as glass or flexible plastics. While FETs based on individual CNTs have already demonstrated excellent static characteristics [1,2], the realization of logic circuits with good static and dynamic performance based on individual-CNT FETs remains a challenge. Bachtold et al. realized 2-input NOR gates by connecting p-channel CNT FETs to external load resistors using coaxial cables and reported a signal delay of 30 msec per stage for a 3-stage unipolar ring oscillator [3]. Javey et al. realized complementary 2-input NAND, AND, NOR and OR gates by connecting p- and n-channel CNT FETs using coaxial cables and measured a delay of 750 µsec for a 3-stage ring oscillator [4]. The only monolithically integrated circuit based transistors utilizing individual carbon nanotubes was reported by Chen et al. who measured a signal delay of 1.9 nsec per stage in a complementary ring oscillator realized on a very long (19 µm) carbon nanotube [5].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122351363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric Al2O3栅极电介质的AlGaN/GaN-on-Si杂化MOS-HFET

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994503

A. Corrion, M. Chen, R. Chu, S. Burnham, S. Khalil, D. Zehnder, B. Hughes, K. Boutros

{"title":"Normally-off gate-recessed AlGaN/GaN-on-Si hybrid MOS-HFET with Al2O3 gate dielectric","authors":"A. Corrion, M. Chen, R. Chu, S. Burnham, S. Khalil, D. Zehnder, B. Hughes, K. Boutros","doi":"10.1109/DRC.2011.5994503","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994503","url":null,"abstract":"GaN-based HFETs offer a combination of high breakdown field, high current densities, and low on-resistance, making them well-suited for power-switching applications. Normally-off FETs are preferred in power switching applications for circuit simplicity and safety. Recently, a new type of normally-off GaN device has been reported: the hybrid metal-oxide-semiconductor (MOS)- or metal-insulator-semiconductor (MIS)-HFET, consisting of an MOS-type structure under the gate for normally-off operation and an HFET-like structure in the access regions for low on-resistance [1–6]. Optimization of the insulator-epi interface and insulator quality is critical for this type of device, since the electrons under gate electrode are in direct contact with the gate insulator. Previous reports of hybrid MOS-HFETs used SiO2 or SiN gate dielectrics deposited by plasma-enhanced chemical vapor deposition (PECVD). However, alternative deposition methods such as atomic layer deposition (ALD) have been shown to result in superior thickness control, uniformity, conformality, and film quality, while ALD high-k gate dielectrics such as Al2O3 have generated significant interest for GaN HFETs due to excellent GaN interface quality. In this work, we fabricated normally-off AlGaN/GaN hybrid MOS-HFETs on (111) Si substrates using gate recess etching combined with an ALD Al2O3 gate dielectric for low gate leakage, low on-resistance, and high breakdown voltage. The gate fabrication process was optimized to reduce the trap density associated with the dielectric and eliminate threshold voltage hysteresis, which can result from slow traps in the dielectric or at the dielectric-epi interface [7]. A three-terminal breakdown voltage (VB) of 1370V was measured at a gate bias of 0 V on a device with a 20 mm gate periphery and a low specific on-resistance (Ron) of 9.0 mΩ-cm2. The resulting VB2/Ron figure of merit of 208 MW/cm2 is among the highest values reported to-date for normally-off GaN-on-Si HFETs.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123450748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Gate capacitance scaling and graphene field-effect transistors with ultra-thin top-gate dielectrics 门电容缩放和石墨烯场效应晶体管与超薄顶栅电介质

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994409

B. Fallahazad, Kayoung Lee, Seyoung Kim, C. Corbet, E. Tutuc

{"title":"Gate capacitance scaling and graphene field-effect transistors with ultra-thin top-gate dielectrics","authors":"B. Fallahazad, Kayoung Lee, Seyoung Kim, C. Corbet, E. Tutuc","doi":"10.1109/DRC.2011.5994409","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994409","url":null,"abstract":"Graphene has emerged recently as an attractive channel material for high frequency analog device applications. High carrier mobility and large gate capacitance are both desirable attributes for such devices. A main obstacle however in depositing thin dielectrics on graphene, with high dielectric constant is its chemical inertness. This obstacle can be overcome by either directly depositing the dielectric, e.g. using sputtering or e-beam evaporation, or by using a seed layer which provides nucleation sites for atomic layer deposition (ALD). The interfacial layer however reduces the gate capacitance and can also impact the quality of the ALD dielectric subsequently grown. Here we provide a systematic study of gate capacitance scaling of graphene field effect transistors with Al2O3 gate dielectric with two seed layers, oxidized aluminum and oxidized titanium. Our results show the oxidized Ti film on graphene provides a smooth surface, which allows us to use a Ti nucleation layer as thin as 6Å, and achieve uniform coverage required for the subsequent ALD. The k-value of the ALD Al2O3 grown on graphene using oxidized Ti as nucleation layer is 12.7, a value 2.5 times larger than the ALD Al2O3 grown using oxidized Al. We demonstrate graphene devices with ultra-thin top gate dielectrics, with EOT values as low as 3.5 nm.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128732830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Aluminum top-gate ZnO nanowire transistors with improved transconductance 具有改进跨导性的铝顶栅ZnO纳米线晶体管

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994518

D. Kalblein, B. Fenk, K. Hahn, U. Zschieschang, K. Kern, H. Klauk

引用次数: 0

Orientation dependent complex bandstructure of Si1−xGex alloys Si1−xGex合金取向相关的复带结构

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994441

A. Ajoy, K. Murali, S. Karmalkar, S. Laux

引用次数: 4

Hole mobility enhancement in uniaxially strained SiGe FINFETs: Analysis and prospects 单向应变SiGe finfet的空穴迁移率增强:分析与展望

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994513

R. Bijesh, I. Ok, M. Baykan, C. Hobbs, P. Majhi, R. Jammy, S. Datta

{"title":"Hole mobility enhancement in uniaxially strained SiGe FINFETs: Analysis and prospects","authors":"R. Bijesh, I. Ok, M. Baykan, C. Hobbs, P. Majhi, R. Jammy, S. Datta","doi":"10.1109/DRC.2011.5994513","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994513","url":null,"abstract":"Experimental and theoretical hole mobility study in uniaxially strained (110)<110> Si0.75Ge0.25 pFINFETs shows that alloy scattering contributes only a small fraction of the overall mobility at 300K but plays a bigger role limiting 77K hole mobility. Increasing the Ge content to 50% increases the strain level. However, the extent of strain relaxation depends on the length of the fin. Fig. 10 shows the measured and projected hole mobility for SiGe FINFETs with 25% and 50% Ge mole fraction. Higher strain induced reduction of effective mass compensates for the increased interface charge density, Dit, in SSGOI0.5 pFINFET and alloy disorder and results in 157% increase in the hole mobility observed at Ns=1×1013 cm−2 and T=300K. Fig. 11 benchmarks the hole mobility in SSGOI0.25 and SSGOI0.5 pFINFETs as a function of electrical oxide thickness (TOXE) and shows its advantage over relaxed Ge channel MOSFETs. However strain relaxation for shorter length fins need to be addressed using careful layout techniques. High mobility combined with excellent short channel behavior make these devices a promising candidate for future technology node.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134099661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3