69th Device Research Conference最新文献

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Total GaN solution to electrical power conversion 电力转换的总氮化镓解决方案
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994505
Y. Wu, R. Coffie, N. Fichtenbaum, Y. Dora, C. Suh, L. Shen, P. Parikh, U. Mishra
{"title":"Total GaN solution to electrical power conversion","authors":"Y. Wu, R. Coffie, N. Fichtenbaum, Y. Dora, C. Suh, L. Shen, P. Parikh, U. Mishra","doi":"10.1109/DRC.2011.5994505","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994505","url":null,"abstract":"We present the first 600V-class, total GaN solution for electrical power conversion applications. A 220V–400V boost converter using a GaN transistor and a GaN diode with fast & clean hard-switched waveforms has been demonstrated. The conversion efficiency was >99.1% at 100 kHz and >98.2% at 800 kHz.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125636133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Monolayer MoS2 transistors - ballistic performance limit analysis 单层MoS2晶体管-弹道性能极限分析
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994421
K. Ganapathi, Y. Yoon, S. Salahuddin
{"title":"Monolayer MoS2 transistors - ballistic performance limit analysis","authors":"K. Ganapathi, Y. Yoon, S. Salahuddin","doi":"10.1109/DRC.2011.5994421","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994421","url":null,"abstract":"To summarize, using ballistic NEGF-based transport simulations, we project the maximum performance achievable with monolayer MoS2 transistors. Our simulations show that these devices can provide (i) excellent switching behavior with very high ON current, (ii) a gm of about 3 mS/µm, and (iii) immunity to short channel effects thanks to the electrostatistically efficient 2-D geometry. We have also investigated the effect of underlap, barrier height and contact resistance on the device performance. We note that while these numbers are representative of the best performance MoS2 transistors can offer, the fact that they are significantly better than those for either state-of-the-art silicon, III–V or graphene makes MoS2 devices promising for future electronic applications.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127993215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electrical pumped integrated III/V laser lattice-matched to a Silicon substrate 电泵浦集成III/V激光晶格与硅衬底相匹配
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994521
B. Kunert, S. Liebich, M. Zimprich, A. Beyer, S. Ziegler, K. Volz, W. Stolz, N. Hossain, S. Jin, S. Sweeney
{"title":"Electrical pumped integrated III/V laser lattice-matched to a Silicon substrate","authors":"B. Kunert, S. Liebich, M. Zimprich, A. Beyer, S. Ziegler, K. Volz, W. Stolz, N. Hossain, S. Jin, S. Sweeney","doi":"10.1109/DRC.2011.5994521","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994521","url":null,"abstract":"The enormous development of Silicon (Si) based integrated circuits (ICs) and micro-electronics is based on the downscaling of semiconductor devices. This driving force, however, is approaching fundamental limitations and therefore new technologies are necessary to guarantee future progress in IC functionalities.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131851632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs 单轴拉伸应变蓄能型栅极全能硅纳米线nmosfet
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994458
M. Najmzadeh, D. Bouvet, W. Grabinski, A. Ionescu
{"title":"Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs","authors":"M. Najmzadeh, D. Bouvet, W. Grabinski, A. Ionescu","doi":"10.1109/DRC.2011.5994458","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994458","url":null,"abstract":"In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ∼400 K and carrier mobility, flat-band and threshold voltages are extracted and investigated.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133480046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Synthesis and applications of graphene for flexible electronics 柔性电子材料石墨烯的合成与应用
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994410
B. Hong
{"title":"Synthesis and applications of graphene for flexible electronics","authors":"B. Hong","doi":"10.1109/DRC.2011.5994410","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994410","url":null,"abstract":"As the paradigm of electronic devices changes toward flexible electronics, the development of new materials that can stand high strains becomes more and more important. In particular, flexible transparent electrodes are essential to develop a new type of displays and solar cells that are flexible, foldable or stretchable. However, the current material for transparent electrodes such as indium tin oxides (ITO) is not suitable as flexible electrodes due to its fragility. Graphene, an atom thick carbon materials, is not only highly transparent and conducting but also extremely flexible, which is expected to replace the use of ITO both for flexible and non-flexible electronics in the future. Recently, a method to produce graphene films in large scale using roll-to-roll process has been developed, and the ITO replacement of touch screen panels was successfully demonstrated. In this talk, the overview of recent progresses in the macroscopic applications of graphene for various macroscopic electronics including flexible light emitting diodes, solar cells, batteries, and thin-film transistors will be presented, and the future directions of graphene-based macroelectronics will be discussed.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114622150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Electrochemical supercapacitor based on flexible pillar graphene nanostructures 基于柔性柱状石墨烯纳米结构的电化学超级电容器
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994429
Jian Lin, J. Zhong, Duoduo Bao, Jennifer Reiber-kyle, W. Wang, V. Vullev, M. Ozkan, C. Ozkan
{"title":"Electrochemical supercapacitor based on flexible pillar graphene nanostructures","authors":"Jian Lin, J. Zhong, Duoduo Bao, Jennifer Reiber-kyle, W. Wang, V. Vullev, M. Ozkan, C. Ozkan","doi":"10.1109/DRC.2011.5994429","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994429","url":null,"abstract":"Here we report the fabrication of high conductive and large surface-area 3D pillar graphene nanostructures (PGN) films from assembly of vertically aligned CNT pillars on flexible copper foils and directly employed for the application in electrochemical double layer capacitance (EDLC) supercapacitor. The fabricated supercapacitor based on PGN films with excellent mechanical flexibility and electrical conductivity has high energy storage capability. The PGN films which were one-step synthesized on flexible copper foil (25 um) by CVD process exhibit high conductivity with sheet resistance as low as 1.6 ohm per square and high mechanical flexibility. The fabricated EDLC supercapacitor based on high surface-area PGN electrodes (563m2/g) shows high performance with high specific capacitance of 330F/g and energy density as high as 45.8Wh/kg. All of these make this 3D graphene/CNTs hybrid carbon nanostructures highly attractive material for high performance supercapacitor and other energy storage material.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114963547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation 介电击穿引起的随时间变化的STT-MRAM性能退化建模
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994447
G. Panagopoulos, C. Augustine, K. Roy
{"title":"Modeling of dielectric breakdown-induced time-dependent STT-MRAM performance degradation","authors":"G. Panagopoulos, C. Augustine, K. Roy","doi":"10.1109/DRC.2011.5994447","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994447","url":null,"abstract":"In recent years, spin-transfer torque magnetoresistive random access memory (STT-MRAM) has gained a lot of interest as a promising memory candidate for future embedded applications. STT-MRAM possesses desirable memory attributes such as excellent readability, writability, stability, non-volatility, and unlimited endurance. Moreover, ITRS reports that STT-MRAM can endure 1015 cycle operations before breakdown [1] thus meeting 10 yrs life-time. As shown in Fig. 1, STT-MRAM bitcell consists of one access transistor and one magnetic tunnel junction (MTJ) (1T-1R). One of the primary reliability concerns in STT-MRAM is the dielectric breakdown of the tunnel junction MgO in the MTJ known as time-dependent dielectric breakdown (TDDB). The thickness of MgO is on the order of 1nm and the voltage across the MTJ during write operation is approximately 0.7V resulting in electric field of ∼10MV/cm across it which can induce TDDB [2–3]. Thus, such high stress conditions can lead to lower breakdown time (TBD) which can go even lower with further MgO thickness scaling. In addition to the hard breakdown (HBD) in MTJ which results in very low MTJ impedance and inability to function as memory, experimental results show that soft breakdowns (SBD) also exists [7,8]. SBDs cause minor degradation in the MTJ resistance and they have shorter average time to appear compared to HBDs. In this paper, we explore in detail the physical mechanism behind both HBD and SBD, and using percolation model we estimate the time dependent degradation in the MTJ performance parameters such as tunneling magneto-resistance (TMR), write current (JC), write-time (TWR) and lifetime (TLIFE).","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Improvement of efficiency in inverted bottom-emission white OLEDs by doping the hole transport layer 掺杂空穴输运层提高反向底发射白色oled的效率
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994431
Hyunkoo Lee, Jeonghun Kwak, Jaehoon Lim, K. Char, Seonghoon Lee, Changhee Lee
{"title":"Improvement of efficiency in inverted bottom-emission white OLEDs by doping the hole transport layer","authors":"Hyunkoo Lee, Jeonghun Kwak, Jaehoon Lim, K. Char, Seonghoon Lee, Changhee Lee","doi":"10.1109/DRC.2011.5994431","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994431","url":null,"abstract":"Recently, it is a critical issue to make larger display panels with low costs in organic light-emitting diodes (OLEDs). However, the uniformity and the cost of low temperature poly Si (LTPS) thin film transistors (TFTs) based backplanes for driving panels as well as the fine metal mask for pixel-patterning obstruct the realization of large-size OLED displays. To overcome these problems, using amorphous silicon (a-Si) TFTs which have high uniformity and cost-efficiency as the backplanes and white OLEDs (WOLEDs) which do not requiring any fine metal mask have been suggested previously. The inverted structure of OLEDs is much suitable rather than the conventional structure for a-Si TFTs because most a-Si TFTs have n-type channel.[1] Here, we demonstrate highly efficient inverted bottom-emission WOLEDs by controlling the balance of electrons and holes injected from electrodes. The maximum external quantum efficiency (E.Q.E.) of inverted WOLEDs was increased from 6.4% to 8.6% (about 34% improvement). To the best of our knowledge, this value is the highest E.Q.E. without other optical light extraction techniques in inverted WOLEDs reported to date.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122152762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Complementary-type graphene inverters operating at room-temperature 在室温下工作的互补型石墨烯逆变器
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994408
Hong-Yan Chen, J. Appenzeller
{"title":"Complementary-type graphene inverters operating at room-temperature","authors":"Hong-Yan Chen, J. Appenzeller","doi":"10.1109/DRC.2011.5994408","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994408","url":null,"abstract":"Graphene has recently emerged as a promising candidate for a number of electronic applications. However, the fact that graphene is a zero band gap material by nature has raised many questions in terms of graphene's usefulness for digital applications. Several recent experimental studies have demonstrated graphene based inverters, but issues remain, such as, low inverter gain (0.044[1], 0.02[2]) and mismatch between input/output voltage levels[1,2]. Li et al.[3,4] reported top-gated complementary-like graphene inverters exhibiting a gain larger than 1. However, all data were obtained at 77K, and the implementation of a p-type and n-type FET was accomplished by relying on the intrinsic dependence of graphene's transfer characteristics on the supply voltage, an effect that is hardly controllable and that poses major problems for further device optimization. In this paper, focusing on inverter characteristics without attempting to build a highly scaled device, we report the first room-temperature, electrostatic doping controlled complementary graphene inverter with a gain larger than one.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125768252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Voltage-controlled spin-wave-based logic gate 基于自旋波的电压控制逻辑门
69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994464
Tian-shi Liu, G. Vignale
{"title":"Voltage-controlled spin-wave-based logic gate","authors":"Tian-shi Liu, G. Vignale","doi":"10.1109/DRC.2011.5994464","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994464","url":null,"abstract":"Spin wave spintronics (also known as magnonics) processes information by propagating spin waves with no charge displaced. Because dissipation is thus minimized this is rapidly becoming an important subject of research within the larger area of spintronics. The logic states in magnonic circuitry can be defined either by the phase or by the amplitude of the spin wave. In both cases, a π-phase shifter plays a crucial role in performing logical operations. The first spin wave logic gate was experimentally demonstrated by Kostylev et al 1. They utilized an inhomogeneous magnetic field to control the phase difference between spin waves propagating in different arms of a Mach-Zehnder interferometer -and thus the amplitude of the output spin wave. Later, Schneider et al 2 and Lee et al 3 developed a complete set of logic gates such as NOR, XOR and AND, based on spin wave interferometry. However, all of theses gates are controlled by a current-induced magnetic field. As the devices shrink down, π-phase shift requires a larger electric current to induce stronger magnetic field, which inevitably increases the power-loss. Therefore, voltage-controlled spin wave electronics becomes an attractive alternative avenue towards nano-scale magnonics, where exchange spin waves are of primary interest.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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