69th Device Research Conference最新文献_第3页

InAs/SiGe on Si nanowire tunneling field effect transistors 硅纳米线隧道场效应晶体管上的InAs/SiGe

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994462

C. Kshirsagar, S. Koester

{"title":"InAs/SiGe on Si nanowire tunneling field effect transistors","authors":"C. Kshirsagar, S. Koester","doi":"10.1109/DRC.2011.5994462","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994462","url":null,"abstract":"Tunneling field-effect transistors (TFETs) are of tremendous interest for advanced logic applications due to their potential for sub-60-mV/dec subthreshold slope which could enable supply voltage scaling beyond what is practical for conventional MOSFETs. However, TFETs based upon tunneling in Si suffer from low on current, ION, and fail to provide steep slope at high current levels. III–V TFETs are more promising due to their potential for high drive current, but the poor gate oxide quality remains a significant challenge. Recently, a hybrid III–V-on-Si approach [1] has been proposed as a potential solution to this problem, whereby the small effective band gap, Egeff, of the InAs/Si heterojunction could increase ION, while preserving the high-quality Si/dielectric interface in the channel. Experimental demonstrations of nanostructured InAs-on-Si Esaki diodes and TFETs suggest this approach is feasible [1],[2]. However, InAs-on-Si heterostructures still exhibit relatively large Egeff (∼ 0.4 eV in unconfined geometries) and quantum effects increase Egeff substantially in confined geometries. In this paper, we provide a simulation analysis of a new device structure, the InAs/SiGe/Si TFET that could overcome this problem by utilizing a compressivelystrained SiGe layer to further decrease Egeff. We show that ION in these devices increases by 5× (at constant Ioff) and further explore the various trade-offs and performance-limiting factors in these devices.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations 具有倾斜磁各向异性的双柱自旋传递扭矩MRAM，用于快速无差错切换和近无干扰读取操作

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994466

N. Mojumder, S. Gupta, K. Roy

{"title":"Dual Pillar Spin Transfer Torque MRAM with tilted magnetic anisotropy for fast and error-free switching and near-disturb-free read operations","authors":"N. Mojumder, S. Gupta, K. Roy","doi":"10.1109/DRC.2011.5994466","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994466","url":null,"abstract":"We propose a three terminal, dual pillar magnetic tunnel junction (MTJ) with tilted magnetic anisotropy for fast and error-free precessional magnetic switching with near-disturb-free magneto-resistive data sensing. Marginal tilting of magnetic anisotropy of the pinned layer in the write-in port enables fast (∼2ns) and error-free magnetic switching, subject to an electric current density of almost 70% lower than that required in a conventional STT-MRAM with perpendicular magnetic anisotropy (PMA). A thicker tunnel barrier is incorporated in the spatially and electrically isolated read-out port for higher tunneling magneto-resistance (TMR) and near-disturb-free read operations. Dual bit line memory architecture with just one access transistor per bit-cell is also proposed. The technology-circuit co-optimization of the proposed one transistor Dual Pillar Spin Transfer Torque (DPSTT) MRAM cell is carried out using effective mass-based spin transport [1] and finite temperature macro-magnetic simulations involving Landau-Lifshitz-Gilbert-Slonczewski (LLGS) equation [2–4]. The proposed DPSTT-MRAM bit-cell outperforms the state-of-the-art 1T-1MTJ STT-MRAM cell in terms of higher cell TMR, single supply voltage for read/write, near-disturb-free data access under parametric process variations with comparable or even lower critical switching current.","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Introduction of ALD Beryllium oxide gate dielectric for III–V MOS devices III-V型MOS器件用ALD氧化铍栅电介质的介绍

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994448

T. Akyol, J. Yum, D. Ferrer, M. Lei, M. Downer, C. Bielawski, T. Hudnall, G. Bersuker, J.C. Lee, S. Banerjee

引用次数: 1

Lateral gate suspended-body carbon nanotube field-effect-transistors with sub-100nm air gap by precise positioning method 采用精确定位方法制备气隙小于100nm的横向栅悬体碳纳米管场效应晶体管

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994482

Ji Cao, A. Ionescu

引用次数: 2

Effects of heavily doped source on the subthreshold characteristics of nanowire tunneling transistors 重掺杂源对纳米线隧道晶体管亚阈值特性的影响

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994415

M. Khayer, R. Lake

引用次数: 3

Fabrication of vertical InAs-Si heterojunction tunnel field effect transistors 垂直InAs-Si异质结隧道场效应晶体管的制备

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994479

H. Schmid, K. Moselund, M. Bjork, M. Richter, H. Ghoneim, C. Bessire, H. Riel

引用次数: 26

60 nm gate length Al2O3 / In0.53Ga0.47As gate-first MOSFETs using InAs raised source-drain regrowth 60 nm栅长Al2O3 / In0.53Ga0.47As栅极优先mosfet采用InAs提高源极漏极再生

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994402

A. Carter, J. Law, E. Lobisser, G. Burek, W. Mitchell, B. Thibeault, A. Gossard, M. Rodwell

{"title":"60 nm gate length Al2O3 / In0.53Ga0.47As gate-first MOSFETs using InAs raised source-drain regrowth","authors":"A. Carter, J. Law, E. Lobisser, G. Burek, W. Mitchell, B. Thibeault, A. Gossard, M. Rodwell","doi":"10.1109/DRC.2011.5994402","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994402","url":null,"abstract":"Given adequately low source/drain (S/D) access resistivity and dielectric interface trap density (R<inf>access</inf> < 50 Ω-µ,1 and D<inf>it</inf> < 2 · 1012 cm−2 eV−1,2 respectively), InGaAs MOSFETs will provide greater on-state current than silicon MOSFETs at the same effective oxide thickness (EOT). The access resistance must be obtained in a self-aligned structure with a contacted gate pitch ∼4 times the physical gate length (L<inf>g</inf>), e.g. 116 nm at 32 nm L<inf>g</inf>,3 while control of short channel effects demands that the S/D region depth be only a fraction of gate length; low-resistance, ultra-shallow fully self-aligned III-V MOS processes must therefore be developed. Here we report a 60 nm L<inf>g</inf> In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFET fabricated in a gate-first process with self-aligned raised InAs S/D access regions formed by MBE regrowth. The devices have a peak drive current of 1.36 mA/µm at V<inf>ds</inf> = 1.25 V and V<inf>gs</inf> = 3 V and an R<inf>on</inf> = 341 ohm-µm. To our knowledge this is the lowest R<inf>on</inf> and smallest L<inf>g</inf> reported to date for In<inf>0.53</inf>Ga<inf>0.47</inf>As surface channel MOSFETs.4","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127008076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on 利用维数实现了尖隧穿场效应晶体管(TFET)的导通

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994496

S. Agarwal, E. Yablonovitch

引用次数: 41

Highly-strained SGOI p-channel MOSFETs fabricated by applying Ge condensation technique to strained-SOI substrates 应用锗凝聚技术在应变soi衬底上制备高应变SGOI p沟道mosfet

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994512

Junkyo Suh, R. Nakane, N. Taoka, M. Takenaka, S. Takagi

{"title":"Highly-strained SGOI p-channel MOSFETs fabricated by applying Ge condensation technique to strained-SOI substrates","authors":"Junkyo Suh, R. Nakane, N. Taoka, M. Takenaka, S. Takagi","doi":"10.1109/DRC.2011.5994512","DOIUrl":"https://doi.org/10.1109/DRC.2011.5994512","url":null,"abstract":"Much attention has recently been paid to MOS channel materials with high mobility and resulting high injection velocity that can increase ION and reduce delay [1]. Among them, ultrathin body SiGe-On-Insulator (SGOI) structure with high compressive strain and high Ge content is a promising channel material for pMOSFETs under future technology nodes. Here, many theoretical studies [2–4] have reported that incorporation of a large amount of compressive strain into SiGe materials is a key technology for boosting the performance. Also, one of promising techniques for fabricating the SGOI structures is Ge condensation technique, composed of epitaxial growth of SiGe layers on SOI substrates and successive thermal oxidation [5, 6]. It is known, however, in Ge condensation using conventional unstrained SOI substrates [5, 7, 8] that strain relaxation occurs when Ge content becomes ∼0.60 and strain significantly decreases with an increase in Ge content. This strain relaxation has been attributed to crystal defect generation during Ge condensation, induced by large strain in the SGOI due to the lattice mismatch between Si and Ge [8–10].","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134211197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High breakdown voltage ZnMgO/In-Ga-Zn-O heterostructure transistors 高击穿电压ZnMgO/In-Ga-Zn-O异质结构晶体管

69th Device Research Conference Pub Date : 2011-06-20 DOI: 10.1109/DRC.2011.5994460

J. Yamaguchi, I. Soga, T. Iwai

引用次数: 1