利用维数实现了尖隧穿场效应晶体管(TFET)的导通

S. Agarwal, E. Yablonovitch
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引用次数: 41

摘要

为了显著降低功耗,需要降低晶体管的工作电压。要做到这一点,基于隧道的晶体管需要依赖于如图1[1]所示的导通态密度。电流只有在传导带和价带重叠时才能流动。如果带边缘是理想的,当带边缘重叠时,人们可能会期望一个无限尖锐的开关。令人惊讶的是,在典型的三维体TFET中,导通的性质实际上是栅极电压的二次函数。然而,如果降低维数,则有可能改善这一点。因此,我们探索了图2所示的各种维度的频带重叠的性质。我们发现,如图2(i)所示的2d-2d pn结使我们更接近于理想阶跃函数。限制pn结的每一边也将显著增加在低电压下的导通状态电导率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Using dimensionality to achieve a sharp tunneling FET (TFET) turn-on
In order to achieve significantly reduced power consumption, the transistor operating voltage needs to be reduced. To do this, a tunneling based transistor needs to rely on the density of states turn-on as shown in Fig 1 [1]. Current can only flow when the conduction and valence bands overlap. If the band edges are ideal, one might expect an infinitely sharp turn on when the band edges overlap. Surprisingly, in a typical 3d bulk TFET, the nature of the turn on is actually quadratic in the gate voltage. Nevertheless, it is possible improve this if dimensionality is reduced. Consequently, we explored the nature of the band overlap for the various dimensionalities shown in Fig 2. We find that a 2d-2d pn junction, as shown in Fig. 2(i) brings us significantly closer to an ideal step function. Confining each side of the pn junction will also significantly increase the on state conductivity at low voltages.
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