Solid State Electronics Letters最新文献_第5页

Architecture of resistive RAM with write driver 带写驱动的电阻式RAM结构

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.01.001

Shashank Kumar Dubey , A. Reddy , Rashi Patel , Master Abz , Avireni Srinivasulu , Aminul Islam

{"title":"Architecture of resistive RAM with write driver","authors":"Shashank Kumar Dubey , A. Reddy , Rashi Patel , Master Abz , Avireni Srinivasulu , Aminul Islam","doi":"10.1016/j.ssel.2020.01.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.01.001","url":null,"abstract":"<div><p>As technological advancements are increasing in the world at a faster rate, the need of miniaturization is also growing parallelly. The scaling of existing MOS technology in nanometre regime has caused some limitations such as drastically increase in leakage current, power consumption and some quantum mechanical effects. This paper provides an insight of an alternative technology which makes use of new circuit element called memristor which can be successfully scaled at a lower nanometre regime. This paper proposes a new READ and WRITE circuitry to facilitate an easier read and write operation. The paper illustrates a transmission gate based 2T1M RRAM bit cell which uses memristor as a memory element and subjects it to process, voltage and temperature (PVT) variations with the aim of reflecting the improvement in performance metrices read and write delay along with the read current variability. The SPICE simulation results reflect that the proposed memory cell has a better stability due to its less read current variability against process variation (such as varying oxide thickness) and is robust with minimal variation in read/write delay with respect to the variations in voltage and temperature. The cell depicts shorter read and write delay compared to NAND and NOR CMOS based flash memories and it has 98.72%,94.53% lesser write time when compared to ambipolar transistor-based memory cell and memristor based content addressable memory (MCAM) respectively. The proposed cell also has 72.5% lesser read time compared to MCAM.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 10-22"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.01.001","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

The Simulation Study on Internal Stress in Multilayer Thermistors during Soldering Process 多层热敏电阻焊接过程内应力的模拟研究

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/J.SSEL.2020.12.003

N. Yu, JuSong Kim, Yong Li, S. C. Pak

引用次数: 0

Impact of back gate work function for enhancement of analog/RF performance of AJDMDG Stack MOSFET 后门功函数对提高AJDMDG堆叠MOSFET模拟/射频性能的影响

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.005

Arighna Basak , Angsuman Sarkar

引用次数: 5

Improving Off-State Breakdown Voltage of a Double-Channel AlGaN/GaN HEMT with Air-Bridge Field Plate and Slant Field Plate 采用气桥场极板和斜场极板提高双通道AlGaN/GaN HEMT的断态击穿电压

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.10.002

Yang-Hua Chang, Jyun-Jhih Wang, Gui-Lin Shen

引用次数: 4

Simulation on the electric field effect of Bi thin film Bi薄膜电场效应的模拟

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.04.001

Lee-Chi Hong , Chieh Chou , Hao-Hsiung Lin

引用次数: 0

Simulation and analysis of the forward bias current–voltage–temperature characteristics of W/4H-SiC Schottky barrier diodes for temperature-sensing applications 温度传感用W/4H-SiC肖特基势垒二极管正向偏置电流-电压-温度特性的仿真与分析

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.08.001

Kamal Zeghdar , Hichem Bencherif , Lakhdar Dehimi , Fortunato Pezzimenti , Francesco G. DellaCorte

引用次数: 3

A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators 一个5位500MS/s闪存ADC与温度补偿的基于逆变器的比较器

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.01.007

Jiangpeng Wang , Wing-Shan Tam , Chi-Wah Kok , Kong-Pang Pun

{"title":"A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators","authors":"Jiangpeng Wang , Wing-Shan Tam , Chi-Wah Kok , Kong-Pang Pun","doi":"10.1016/j.ssel.2020.01.007","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.01.007","url":null,"abstract":"<div><p>In this paper, a 5-bit 500MS/s flash analog-to-digital converter (ADC) with temperature-compensated inverter-based comparators is proposed. In the proposed ADC, a complementary-average system structure is adopted. Based on this structure, inverter-based comparators are used to reduce the power consumption. However, conventional inverter-based comparators suffer from switching threshold variation when the temperature changes, which degrades the SNDR performance of the whole ADC. To tackle this problem, a temperature-compensated inverter-based comparator is proposed. Furthermore, an encoder with majority-3 bubble error correction is used in the proposed ADC to reduce bubble errors. To verify the proposed design, a prototype ADC is implemented in a 0.18 µm process. Measurements at room temperature show that the SNDR and SFDR of the proposed prototype are 29.6 dB and 34.92 dB, with a resulting ENOB of 4.62 bits. It achieves an DNL and INL of +0.33 LSB /−0.54 LSB and +0.27 LSB/−0.33 LSB, respectively, and consumes 6 mW from a 1.8-V supply. At 0 °C and 60 °C, the ADC maintains a close performance.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 1-9"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.01.007","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91774711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Investigation on 10-nm channel-length n-type junctionless variable barrier nanowire transistor 10nm通道长度n型无结变势垒纳米线晶体管的研究

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.06.001

Keng-Ming Liu, Sheng-Hong Liao

引用次数: 1

Corrigendum to ’An Integrator Circuit Using Voltage Difference Transconductance Amplifier’ [Solid State Electronics Letters 1 (2019) 10-14] “使用电压差跨导放大器的积分器电路”的勘误表[固态电子快报1 (2019)10-14]

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.001

引用次数: 0

Fast and energy efficient full adder circuit using 14 CNFETs 使用14个cnfet的快速节能全加法器电路

Solid State Electronics Letters Pub Date : 2020-01-01 DOI: 10.1016/j.ssel.2020.09.002

J. Saini, Avireni Srinivasulu, R. Kumawat

引用次数: 2