Investigation on 10-nm channel-length n-type junctionless variable barrier nanowire transistor

Abstract

In this paper we simulated and investigated the device characteristics of a novel device structure derived from the junctionless (JL) gate-all-around (GAA) nanowire (NW) transistor, variable barrier transistor (VBT). Basically, VBT is accomplished by the local constrictions at both ends of the channel region of the JL GAA NW transistor. The device simulation is performed based on the non-equilibrium Green's function (NEGF) approach provided by the 3D TCAD device simulator, Atlas. The simulation results suggest the JL VBT can have larger ON/OFF current ratio than that of the JL GAA NW transistor as long as the constriction (or barrier) is properly designed.