Solid State Electronics Letters最新文献

A 1.3-mW 73.3-dB DR 10-MHz Bandwidth CT Delta-Sigma Modulator with a Charge-Recycled SC DAC and 52.7-dB Alias Rejection 一种1.3 mw 73.3 db DR 10mhz带宽CT Delta-Sigma调制器，具有电荷回收SC DAC和52.7 db别名抑制

Solid State Electronics Letters Pub Date : 2022-01-01 DOI: 10.1016/j.ssel.2023.02.001

Hetong Wang, Yang Zhang, K. Pun

引用次数: 0

Design of Convex Corner Compensation Pattern in Manufacturing of Si Diaphragms 硅膜片加工中凸角补偿模式的设计

Solid State Electronics Letters Pub Date : 2022-01-01 DOI: 10.1016/j.ssel.2022.06.001

N. Yu, C. Jon, KyongIl Chu, KumJun Ryang

引用次数: 0

A capacitor-free fast-response low-dropout voltage regulator 一种无电容快速响应低差稳压器

Solid State Electronics Letters Pub Date : 2022-01-01 DOI: 10.1016/j.ssel.2022.12.001

Wing Shan Tam , Yee Wei Law , Chi Wah Kok

引用次数: 0

Empirical Study of the Cut-Off Frequency of Multi-Finger Nanometer MOS Transistor 多指纳米MOS晶体管截止频率的实证研究

Solid State Electronics Letters Pub Date : 2022-01-01 DOI: 10.1016/j.ssel.2023.05.001

Wing-Shan Tam, Chi-Wah Kok

引用次数: 0

A 1.3-mW 73.3-dB DR 10-MHz Bandwidth CT Delta-Sigma Modulator with a Charge-Recycled SC DAC and 52.7-dB Alias Rejection 一种1.3 mw 73.3 db DR 10mhz带宽CT Delta-Sigma调制器，具有电荷回收SC DAC和52.7 db别名抑制

Solid State Electronics Letters Pub Date : 2022-01-01 DOI: 10.1016/j.ssel.2023.02.001

Hetong Wang, Yang Zhang, Kong-Pang Pun

{"title":"A 1.3-mW 73.3-dB DR 10-MHz Bandwidth CT Delta-Sigma Modulator with a Charge-Recycled SC DAC and 52.7-dB Alias Rejection","authors":"Hetong Wang, Yang Zhang, Kong-Pang Pun","doi":"10.1016/j.ssel.2023.02.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2023.02.001","url":null,"abstract":"<div><p>A multi-level DAC with high intrinsic linearity and low power consumption enables a greater design space for wide-band continuous-time (CT) Delta-Sigma modulators (DSMs). This manuscript introduces an intrinsically highly linear 5-level switched-capacitor (SC) DAC with a power-saving charge recycling technique for wideband CT DSMs. We also adopt a distinct modulator architecture that places a large low-pass filter (LPF) capacitor at the input of the first amplifier. This architecture substantially enhances the modulator’s power efficiency and restores the modulator’s alias rejection ratio (AR) in the presence of an SC type of DAC. To validate the proposed techniques, a DSM prototype with a 10-MHz bandwidth and 800 MHz sampling rate (<span><math><msub><mi>f</mi><mi>s</mi></msub></math></span>) is fabricated in a 65-nm CMOS technology. Consuming 1.3 mW from a 1.2-V supply, the prototype achieves a peak signal-to-noise-plus-distortion ratio of 72.3 dB and a dynamic range of 73.3 dB in experiments. The corresponding Warden’s and Schreier’s figures of merits are 19.3 fJ/conv-step and 171.2 dB, respectively. The measured ARs are 52.7 dB and 54.3 dB at <span><math><msub><mi>f</mi><mi>s</mi></msub></math></span> and <span><math><mrow><mn>2</mn><msub><mi>f</mi><mi>s</mi></msub></mrow></math></span>, respectively. The DSM further tolerates an rms clock jitter of 11 ps.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"4 ","pages":"Pages 15-29"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2589208823000017/pdfft?md5=16abf7b3f7488781b9d5719ebfb78734&pid=1-s2.0-S2589208823000017-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91630249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Convex Corner Compensation Pattern in Manufacturing of Si Diaphragms 硅膜片加工中凸角补偿模式的设计

Solid State Electronics Letters Pub Date : 2022-01-01 DOI: 10.1016/j.ssel.2022.06.001

Nam Chol Yu , Chung-Hyok Jon , KyongIl Chu , KumJun Ryang

引用次数: 0

Double Edge-Triggered Half-Static Clock-Gating D-Type Flip-Flop 双边缘触发半静态时钟门控d型触发器

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.08.001

Wing-Kong Ng, Wing-Shan Tam, C. Kok

引用次数: 1

A Current Comparison Based Voltage Supervisory Circuit with On-Chip Detection Voltage Trimming 基于电流比较的片上检测电压微调电压监控电路

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.07.001

Wing-Kong Ng, Wing-Shan Tam, C. Kok

引用次数: 1

Multi-layer Perceptron based Comparative Analysis between CNTFET and Quantum Wire FET for Optimum Design Performance 基于多层感知器的CNTFET与量子线FET优化设计性能的比较分析

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.12.003

Arpan Deyasi , Arup Kumar Bhattacharjee , Soumen Mukherjee , Angsuman Sarkar

{"title":"Multi-layer Perceptron based Comparative Analysis between CNTFET and Quantum Wire FET for Optimum Design Performance","authors":"Arpan Deyasi , Arup Kumar Bhattacharjee , Soumen Mukherjee , Angsuman Sarkar","doi":"10.1016/j.ssel.2021.12.003","DOIUrl":"10.1016/j.ssel.2021.12.003","url":null,"abstract":"<div><p>A novel classification technique is applied for identifying carbon nanotube FET and quantum wire FET based on their electrical characteristics and percentage error is estimated using multi-layer perceptron analysis to justify the accuracy of computation. Two different cross-validation methods, namely decision table and multilayer perceptron (MLP) are applied on same data set of both the devices, and results speak about higher accuracy when MLP is performed. Also, for different testing-training set of data, MLP performs far better than conventional decision table approach; when correlation coefficient, mean absolute error, root mean squared error, relative absolute error and root relative squared error are computed. For comparative study, similar geometrical configuration, and equivalent biasing arrangement of both the devices are assumed, and identical number of iterations is performed for equal subsets. Results speak supremacy of MLP technique applied for classification and identification of nanometric devices based on their electronic attributes.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"3 ","pages":"Pages 42-52"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2589208821000119/pdfft?md5=476b086fead1dae48bef896ab9c1e6a0&pid=1-s2.0-S2589208821000119-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77174944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A Current Comparison Based Voltage Supervisory Circuit with On-Chip Detection Voltage Trimming 基于电流比较的片上检测电压微调电压监控电路

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.07.001

Wing-Kong Ng , Wing-Shan Tam , Chi-Wah Kok

{"title":"A Current Comparison Based Voltage Supervisory Circuit with On-Chip Detection Voltage Trimming","authors":"Wing-Kong Ng , Wing-Shan Tam , Chi-Wah Kok","doi":"10.1016/j.ssel.2021.07.001","DOIUrl":"https://doi.org/10.1016/j.ssel.2021.07.001","url":null,"abstract":"<div><p>A low power current comparison based voltage detector with on-chip detection voltage trimming is proposed in this paper. The proposed trimming technique achieves both detection voltage trimming and detection voltage accuracy trimming. The performance of the proposed circuit is validated by simulation using a 0.5 <span><math><mrow><mi>μ</mi></mrow></math></span>m CMOS process. A short power-on rising time (<span><math><msub><mi>t</mi><mrow><mi>r</mi><mi>i</mi><mi>s</mi><mi>e</mi></mrow></msub></math></span>) of less than 1 ms can be achieved due to the utilization of current comparison technique. Trimming accuracy on the detection voltage at <span><math><mo>±</mo></math></span>1.875% is obtained. The proposed circuit consumes 140 <span><math><mrow><mi>μ</mi></mrow></math></span>W at supply voltage of 5 V. The overall active silicon area of the proposed circuit is 27900 <span><math><mrow><mi>μ</mi></mrow></math></span><span><math><msup><mrow><mtext>m</mtext></mrow><mn>2</mn></msup></math></span>, which is comparable with that of other reported circuits without trimming functions. The proposed circuit is suitable for the application in a variety of power management application where energy efficiency is a consideration.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"3 ","pages":"Pages 5-10"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2589208821000089/pdfft?md5=c5f7dc9a0b463f120a4e972db3f9586f&pid=1-s2.0-S2589208821000089-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91691741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0