Solid State Electronics Letters最新文献_第8页

Modeling the negative capacitance effect in dispersive organic materials using modified Drude theory 用修正的德鲁德理论模拟分散性有机材料的负电容效应

Solid State Electronics Letters Pub Date : 2019-07-01 DOI: 10.1016/j.ssel.2020.01.005

You-Lin Wu , Jing-Jenn Lin , H.L. Kwok

引用次数: 1

Performance analysis of GaN-based micro light-emitting diodes by laser lift-off process gan基微发光二极管的激光提升性能分析

Solid State Electronics Letters Pub Date : 2019-07-01 DOI: 10.1016/j.ssel.2019.06.001

Li Sheng-Hui , Lin Chia-Ping , Fang Yen-Hsiang , Kuo Wei-Hung , Wu Ming-Hsien , Chao Chu-Li , Horng Ray-Hua , Su Guo-Dung J.

引用次数: 9

Analysis and modeling of sequential circuits in QCA nano computing: RAM and SISO register study QCA纳米计算中顺序电路的分析和建模:RAM和SISO寄存器的研究

Solid State Electronics Letters Pub Date : 2019-07-01 DOI: 10.1016/j.ssel.2019.11.004

Md. Abdullah-Al-Shafi , Rahman Ziaur

{"title":"Analysis and modeling of sequential circuits in QCA nano computing: RAM and SISO register study","authors":"Md. Abdullah-Al-Shafi , Rahman Ziaur","doi":"10.1016/j.ssel.2019.11.004","DOIUrl":"10.1016/j.ssel.2019.11.004","url":null,"abstract":"<div><p>Quantum-dot cellular automata (QCA) is a foremost archetype of field-coupled nanoscale devices. It is a non-von-Neumann, minimal energy dissipated model for conventional nano computing by transistor free logic. The field-coupled nanoscale models rely on limited field connections among nanoscale building modules which are organized in forms to complete convenient assessments. A fundamental device in QCA is termed as a cell is created from a structure of coupled dots by a few flexible charges and the charge arrangement initiates a bit, and quantum charge channeling inside a squared cell permits device shifting. QCA operation approves extreme device thicknesses, room temperature implementation, and higher switching speeds. We propose an inventive design of two commonly used sequential circuits, namely random access memory (RAM) and serial-in/serial-out (SISO) register in this study. Noteworthy enhancements in terms of extent, cell intricacy, latency, and cost have been attained in both designs. Thorough performance assessment and analysis are achieved in several aspects to substantiate the designed circuits having an outstanding operation in contrast to existing studies. QCADesigner and QCAPro tools have been utilized to confirm the precise functionality of the outlined architectures.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"1 2","pages":"Pages 73-83"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2019.11.004","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75447858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Latch-up issue of drain metal connection split in test circuit with 3D TCAD simulation analysis in CMOS application 用三维TCAD仿真分析了测试电路中漏极金属连接劈裂的锁存问题

Solid State Electronics Letters Pub Date : 2019-01-01 DOI: 10.1016/j.ssel.2019.04.001

Chiang Chun, Chang Ping-Chen, Tang Tien-Hao, Su Kuan-Cheng

引用次数: 1

A constant Q-factor notch filter using voltage difference transconductance amplifier 采用压差跨导放大器的恒q因子陷波滤波器

Solid State Electronics Letters Pub Date : 2019-01-01 DOI: 10.1016/j.ssel.2019.05.001

K. Roja , K.M. Santhoshini , M. Sarada , Avireni Srinivasulu

引用次数: 2

An integrator circuit using voltage difference transconductance amplifier 一种采用压差跨导放大器的积分器电路

Solid State Electronics Letters Pub Date : 2019-01-01 DOI: 10.1016/j.ssel.2018.08.001

K. Malathi Santhoshini , Sarada Musala , Srinivasulu Avireni

引用次数: 3

Influence of electron quantum confinement on the strength of carbon nanotube bundles 电子量子约束对碳纳米管束强度的影响

Solid State Electronics Letters Pub Date : 2019-01-01 DOI: 10.1016/j.ssel.2018.09.001

Lucian D. Filip , Valeriu Filip

引用次数: 2

Current collapse scaling in GaN/AlGaN/SiC high electron mobility transistors GaN/AlGaN/SiC高电子迁移率晶体管的电流坍缩缩放

Solid State Electronics Letters Pub Date : 2019-01-01 DOI: 10.1016/j.ssel.2019.04.002

D.S. Rawal, Amit, Sunil Sharma, Sonalee Kapoor, Robert Laishram, Seema Vinayak

{"title":"Current collapse scaling in GaN/AlGaN/SiC high electron mobility transistors","authors":"D.S. Rawal, Amit, Sunil Sharma, Sonalee Kapoor, Robert Laishram, Seema Vinayak","doi":"10.1016/j.ssel.2019.04.002","DOIUrl":"10.1016/j.ssel.2019.04.002","url":null,"abstract":"<div><p>This study reports the scaling of current collapse in GaN/AlGaN HEMTs with respect to the un-passivated gate drain distance on the gate edge. The source drain current reduction increased from 4 mA to 28 mA, when un-passivated gap increased from 200 nm to 600 nm respectively mainly due to virtual gate formation at gate edge as a result of applied large reverse bias between the gate/drain electrodes. The length of virtual gate is a function of un-passivated gap that modifies the lateral electric field between gate-drain region and results in variable current reduction due to variation in available traps with gap. The simulated E-field distribution is found to vary strongly with the un-passivated gap up to 200 nm and weakly thereafter. The HEMT knee voltage shifted from 0.5 V to 1.2 V when gap is increased from 200 nm to 600 nm respectively due to electric field distribution modification and hence electron trapping in the un-passivated gap resulting in increased device on-resistance (R<sub>on</sub>). The current collapse finally resulted in reduction of device saturated RF power to 1.2 W/mm at 2.2 GHz for HEMT with an un-passivated gap of 600 nm.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"1 1","pages":"Pages 30-37"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2019.04.002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81523340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Design methodology of double nulling resistors nested-Miller compensation of multistage amplifier 多级放大器双零化电阻嵌套米勒补偿设计方法

Solid State Electronics Letters Pub Date : 2019-01-01 DOI: 10.1016/j.ssel.2018.06.001

Wing-Shan Tam, Chi-Wah Kok

引用次数: 3