K. Malathi Santhoshini , Sarada Musala , Srinivasulu Avireni
{"title":"An integrator circuit using voltage difference transconductance amplifier","authors":"K. Malathi Santhoshini , Sarada Musala , Srinivasulu Avireni","doi":"10.1016/j.ssel.2018.08.001","DOIUrl":null,"url":null,"abstract":"<div><p>This paper illustrates a novel design of voltage-mode Integrator using the active element, namely Voltage Difference Transconductance Amplifier (VDTA). The proposed circuit avails one VDTA element and a single capacitor. This provides more beneficial for the fabrication of ICs in VLSI design. The designed circuit works with ±0.9 V supply voltage, uses a bias current of order 150 µA and also its amplitude is electronically tunable with the bias current. The proposed circuit is designed in a gpdk 180 nm CMOS process using a Cadence Virtuoso tool and also has the power dissipation of order 270 µW. The simulation results are verified experimentally with the commercially available ICs LM13700.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"1 1","pages":"Pages 10-14"},"PeriodicalIF":0.0000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2018.08.001","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid State Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2589208818300048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper illustrates a novel design of voltage-mode Integrator using the active element, namely Voltage Difference Transconductance Amplifier (VDTA). The proposed circuit avails one VDTA element and a single capacitor. This provides more beneficial for the fabrication of ICs in VLSI design. The designed circuit works with ±0.9 V supply voltage, uses a bias current of order 150 µA and also its amplitude is electronically tunable with the bias current. The proposed circuit is designed in a gpdk 180 nm CMOS process using a Cadence Virtuoso tool and also has the power dissipation of order 270 µW. The simulation results are verified experimentally with the commercially available ICs LM13700.