Solid State Electronics Letters最新文献_第2页

JFET Region Design Trade-Offs of 650 V 4H-SiC Planar Power MOSFETs 650 V 4H-SiC平面功率mosfet的JFET区域设计权衡

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.12.001

Tianshi Liu , Shengnan Zhu , Arash Salemi , David Sheridan , Marvin H. White , Anant K. Agarwal

{"title":"JFET Region Design Trade-Offs of 650 V 4H-SiC Planar Power MOSFETs","authors":"Tianshi Liu , Shengnan Zhu , Arash Salemi , David Sheridan , Marvin H. White , Anant K. Agarwal","doi":"10.1016/j.ssel.2021.12.001","DOIUrl":"10.1016/j.ssel.2021.12.001","url":null,"abstract":"<div>650 V silicon carbide (SiC) power MOSFETs with various JFET region design have been successfully fabricated on 6-inch wafers in a state-of-the-art commercial SiC foundry. The trade-offs between the performance and reliability of the 650 V MOSFETs are studied. In particular, the impact of the JFET region design on the reliability of the SiC MOSFETs and ON-resistance is studied through TCAD simulations and device characterizations. Simulations show that narrower JFET width lowers the electric field at the center of the JFET region and can potentially mitigate device failures under high-temperature reverse bias (HTRB) test with a penalty of higher ON-resistance. It is experimentally demonstrated with the fabricated MOSFETs that the ON-resistance can be reduced with higher JFET region doping and tighter layout design. Compared with recently published studies on 600 V class SiC power MOSFETs, we report the lowest specific ON- resistance (Ron,sp) of 2.06 mΩ · cm2 (further reducible through tighter layout design) while having a narrow JFET region for device reliability.</div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"3 ","pages":"Pages 53-58"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2589208821000090/pdfft?md5=8391dd054b4d1da093f6dcec0cb2fe0a&pid=1-s2.0-S2589208821000090-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78247628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Double Edge-Triggered Half-Static Clock-Gating D-Type Flip-Flop 双边缘触发半静态时钟门控d型触发器

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.08.001

Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok

引用次数: 1

Digital Logic Implementation of Li-ion Battery Protector 锂离子电池保护器的数字逻辑实现

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2022.02.001

Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok

引用次数: 1

Enhanced Performance Double-gate Junction-less Tunnel Field Effect Transistor for Bio-Sensing Application 用于生物传感的增强型双栅无结隧道场效应晶体管

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.12.005

Isukapalli Vishnu Vardhan Reddy , Suman Lata Tripathi

{"title":"Enhanced Performance Double-gate Junction-less Tunnel Field Effect Transistor for Bio-Sensing Application","authors":"Isukapalli Vishnu Vardhan Reddy , Suman Lata Tripathi","doi":"10.1016/j.ssel.2021.12.005","DOIUrl":"https://doi.org/10.1016/j.ssel.2021.12.005","url":null,"abstract":"<div>In this work, a double gate junction-less tunnel FET (DG-JLTFET) has been evaluated for biosensing applications. Tunnelling is the concept in JLTFET which is a heavily doped JL transistor, by decreasing the barrier length between the source and channel of the device which is easily used for switching (ON and OFF) purpose. Based on the research and simulation so far on JLTFET, this has achieved a greater performance when compared to that of MOSFET. JLTFET with more dielectric (k) and low K spacers will give an ON current (0.1 mA/µm) for gate voltage 3V and for off current of (10−15 A/ µm) and performance with Ion/Ioff ratio at 1012 and subthreshold swing with 60 mV/dec is obtained at 20 nm length of the gate at room temperature. So, JLTFET is a better device for switching performance. The evaluation of device performance is also done based on different cavity thicknesses and different dielectric constants. Including these parameters, double gate-pocket-junction-less TFET is highly used in biosensor applications. In the following, we demonstrate high performance based on pocket region which is introduced to implement in JLTFET for biosensor label-free detection</div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"3 ","pages":"Pages 19-26"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2589208821000132/pdfft?md5=d42b49f32f1f8c586dd120365c82fd4d&pid=1-s2.0-S2589208821000132-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136559736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Capacitor-Reused 2b/Cycle Active-Passive Second-order Noise-Shaping SAR ADC 一种电容复用的2b/周期主-被动二阶噪声整形SAR ADC

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.12.006

Xiao Wang, Hetong Wang, Kong-Pang Pun

引用次数: 0

Computational Study of Adsorption behavior of CH4N2O and CH3OH on Fe decorated MoS2 monolayer Fe修饰MoS2单层吸附CH4N2O和CH3OH行为的计算研究

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.12.002

Bibek Chettri , Abinash Thapa , Sanat Kumar Das , Pronita Chettri , Bikash Sharma

{"title":"Computational Study of Adsorption behavior of CH4N2O and CH3OH on Fe decorated MoS2 monolayer","authors":"Bibek Chettri , Abinash Thapa , Sanat Kumar Das , Pronita Chettri , Bikash Sharma","doi":"10.1016/j.ssel.2021.12.002","DOIUrl":"10.1016/j.ssel.2021.12.002","url":null,"abstract":"<div>In this paper, we report the Fe doped MoS2 monolayer to improve the gas sensing properties. We investigated the electronic properties of Fe doped MoS2 for sensing Urea and Methanol using Density Functional Theory (DFT). Non-Equilibrium Green's Function (NEGF) was used to calculate the transport properties of the aforementioned nanomaterials. The absorption energy, charge transfer, bandstructure, Density of States (DOS), Projected Density of States (PDOS), I-V characteristics, recovery time and sensitivity of urea and methanol gas molecules on Fe doped MoS2 were all investigated. As a result, we observed the tremendous change in the electrical and chemical activity of Fe doped MoS2 for the adsorption of urea and methanol. After the substitution of the Fe atom in the MoS2 monolayer, the magnetic property was observed. In comparison to pristine MoS2 and Fe doped MoS2, the bandgap revealed an improvement in conduction property in adsorbed molecules. The outcome was also confirmed by DOS and PDOS. The Fe doped MoS2 for urea and methanol adsorption, the I-V curve shows a linear increase in current for bias voltage up to 1.9 V, then a quick fall in current after increasing a few volts. The relative resistance state of the Fe doped MoS2 based sensor is better, indicating that it can be used as a sensor. At 2 V, the sensitivity for methanol and urea was 82 % and 77.5 %, respectively. For the methanol configuration, the quicker desorption time was calculated to be 0.00015 µs. Our results demonstrate that Fe doped MoS2 is a promising candidate for a low-cost, stable gas sensor.</div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"3 ","pages":"Pages 32-41"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2589208821000107/pdfft?md5=7e95df2fe0e5213076d6a4f423f8a953&pid=1-s2.0-S2589208821000107-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72863074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Design of CMOS Class AB Bridged Audio Amplifier: A Tutorial CMOS AB类桥接音频放大器设计教程

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2022.03.001

Wing Shan Tam, Chi Wah Kok

{"title":"Design of CMOS Class AB Bridged Audio Amplifier: A Tutorial","authors":"Wing Shan Tam, Chi Wah Kok","doi":"10.1016/j.ssel.2022.03.001","DOIUrl":"10.1016/j.ssel.2022.03.001","url":null,"abstract":"<div>This article presents a tutorial on the design of CMOS Class AB bridged audio amplifier. High power efficiency is achieved by using a bridged output stage. An added advantage of the bridged amplifier is that the output stage can operate without the use of any capacitor, which supports the circuit to be operated under single rail power supply. An example of 3 <math><msub><mtext>W</mtext><mrow><mi>R</mi><mi>M</mi><mi>S</mi></mrow></msub></math> audio amplifier with <math><mrow><mn>3</mn><mspace></mspace><mrow><mstyle><mi>Ω</mi></mstyle></mrow></mrow></math> load is presented in this tutorial together with detail analytical analysis to demonstrate how to design a similar CMOS audio amplifier. The design example is simulated with a commercial 0.5 <math><mi>μ</mi></math>m CMOS process together with measurement results from fabricated silicon to sustain the presented design methodology. The fabricated amplifiers can achieve low quiescent power at 33 mW, and a wide peak-to-peak output voltage swing of 8.5 Vpp subject to a 5 V supply. The THD of the amplifier is measured to be smaller than 10<math><mo>%</mo></math>.</div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"3 ","pages":"Pages 70-79"},"PeriodicalIF":0.0,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2589208822000023/pdfft?md5=fea94818b4243e212b164125eeadfe10&pid=1-s2.0-S2589208822000023-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77734432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Tutorial on Resistor Trimming 电阻器微调教程

Solid State Electronics Letters Pub Date : 2021-12-01 DOI: 10.1016/j.ssel.2021.12.004

Wing Shan Tam, Chi Wah Kok

引用次数: 0

Nano-pillars metasurface modelled for perfect absorption at specific wavelengths in infrared spectral regime 纳米柱超表面模型的完美吸收在特定波长的红外光谱制度

Solid State Electronics Letters Pub Date : 2020-12-04 DOI: 10.1016/j.ssel.2020.11.002

R. Tomescu, C. Kusko, D. Cristea, Ramona Calinoiu, C. Parvulescu

引用次数: 5

Improving Off-State Breakdown Voltage of a Double-Channel AlGaN/GaN HEMT with Air-Bridge Field Plate and Slant Field Plate 采用气桥场极板和斜场极板提高双通道AlGaN/GaN HEMT的断态击穿电压

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.10.002

Yang-Hua Chang, Jyun-Jhih Wang, Guilin Shen

引用次数: 4