Double Edge-Triggered Half-Static Clock-Gating D-Type Flip-Flop

A double edge-triggered D-type flip flop includes a half-static clock gating circuit is presented in this paper. Two dynamic latches that each responses to the rising and falling edges of the gated clock are connected in parallel to a half-static latch, which captures the data signal in response to both rising and falling edges of the clock signal. This flip flop topology helps to improve the race tolerance, energy efficiency and circuit compactness. The flip flop is simulated with HSPICE using commercially 0.18 µm CMOS technology. The simulation results presented in this paper showed that it can achieve a 4 Gbits/sec data rate with 96% redundant power reduction when compared to other double edge-triggered D-type flip flop in literature.