JFET Region Design Trade-Offs of 650 V 4H-SiC Planar Power MOSFETs

Tianshi Liu , Shengnan Zhu , Arash Salemi , David Sheridan , Marvin H. White , Anant K. Agarwal
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引用次数: 3

Abstract

650 V silicon carbide (SiC) power MOSFETs with various JFET region design have been successfully fabricated on 6-inch wafers in a state-of-the-art commercial SiC foundry. The trade-offs between the performance and reliability of the 650 V MOSFETs are studied. In particular, the impact of the JFET region design on the reliability of the SiC MOSFETs and ON-resistance is studied through TCAD simulations and device characterizations. Simulations show that narrower JFET width lowers the electric field at the center of the JFET region and can potentially mitigate device failures under high-temperature reverse bias (HTRB) test with a penalty of higher ON-resistance. It is experimentally demonstrated with the fabricated MOSFETs that the ON-resistance can be reduced with higher JFET region doping and tighter layout design. Compared with recently published studies on 600 V class SiC power MOSFETs, we report the lowest specific ON- resistance (Ron,sp) of 2.06 mΩ · cm2 (further reducible through tighter layout design) while having a narrow JFET region for device reliability.

650 V 4H-SiC平面功率mosfet的JFET区域设计权衡
具有各种JFET区域设计的650 V碳化硅(SiC)功率mosfet已在最先进的商用SiC铸造厂的6英寸晶圆上成功制造。研究了650 V mosfet的性能和可靠性之间的权衡。特别是,通过TCAD仿真和器件表征,研究了JFET区域设计对SiC mosfet可靠性和导通电阻的影响。模拟结果表明,较窄的JFET宽度降低了JFET区域中心的电场,并且可以潜在地减轻高温反向偏置(HTRB)测试中器件的故障,但代价是更高的导通电阻。实验结果表明,较高的JFET区域掺杂和更紧凑的布局设计可以降低导通电阻。与最近发表的600 V级SiC功率mosfet的研究相比,我们报告了最低的比on -电阻(Ron,sp)为2.06 mΩ·cm2(通过更紧凑的布局设计进一步减小),同时具有狭窄的JFET区域,以提高器件可靠性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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