A Capacitor-Reused 2b/Cycle Active-Passive Second-order Noise-Shaping SAR ADC

Abstract

In this manuscript, a novel 2nd-order noise-shaping successive-approximation register (NS-SAR) analog-to-digital converter (ADC) is introduced for potential application in wideband continuous-time (CT) $\Delta \Sigma$ modulators. The proposed NS-SAR employs a special active-passive residue filter that reuses the capacitor of the reference digital-to-analogue converter (DAC) of the SAR. Compared to the conventional NS-SAR that uses an active residue filter, the proposed approach saves one power-hungry amplifier and four replica DACs. An asynchronous 2b/cycle conversion scheme is adopted for a reduced excessive loop delay (ELD) in the modulator. Transistor-level simulations in a 65nm CMOS process are presented to demonstrate the principle of the proposed NS-SAR.