Solid State Electronics Letters最新文献_第4页

Structural optimization and miniaturization for Split-Gate Trench MOSFETs with 60 V breakdown voltage 60 V击穿电压的分栅沟槽mosfet结构优化与小型化

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.01.004

Yu-Chin Lee, Jyh-Ling Lin

引用次数: 1

An N-Channel Band-to-Band Tunneling Flash Memory Design Optimization 一种n通道带对带隧道式闪存设计优化

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2021.02.001

Wing-Kong Ng, Wing-Shan Tam, Chi-Wah Kok

引用次数: 0

Designing the Topology of a Unipolar Pulsed-DC Power Supply using the Open-source Scilab/Xcos Software for a Low-cost Plasma Etcher 基于开源Scilab/Xcos软件的低成本等离子体蚀刻器单极脉冲直流电源拓扑设计

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.05.001

Samuel Husin Surya Mandala, M. Januar, Bei Liu, Kou-Chen Liu

引用次数: 0

Fast and energy efficient full adder circuit using 14 CNFETs 使用14个cnfet的快速节能全加法器电路

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.09.002

Jitendra Kumar Saini , Avireni Srinivasulu , Renu Kumawat

{"title":"Fast and energy efficient full adder circuit using 14 CNFETs","authors":"Jitendra Kumar Saini , Avireni Srinivasulu , Renu Kumawat","doi":"10.1016/j.ssel.2020.09.002","DOIUrl":"https://doi.org/10.1016/j.ssel.2020.09.002","url":null,"abstract":"<div><p>With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (V<sub>DD</sub>) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (D<sub>CNT</sub>) and threshold voltage (V<sub>th</sub>) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 67-78"},"PeriodicalIF":0.0,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.09.002","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91761617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

An N-Channel Band-to-Band Tunneling Flash Memory Design Optimization 一种n通道带对带隧道式闪存设计优化

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/J.SSEL.2021.02.001

Wing-Kong Ng, Wing-Shan Tam, C. Kok

引用次数: 0

Corrigendum to ’An Integrator Circuit Using Voltage Difference Transconductance Amplifier’ [Solid State Electronics Letters 1 (2019) 10-14] “使用电压差跨导放大器的积分器电路”的勘误表[固态电子快报1 (2019)10-14]

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.001

引用次数: 0

Impact of back gate work function for enhancement of analog/RF performance of AJDMDG Stack MOSFET 后门功函数对提高AJDMDG堆叠MOSFET模拟/射频性能的影响

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/J.SSEL.2020.12.005

A. Basak, A. Sarkar

引用次数: 5

Corrigendum to: An Integrator Circuit Using Voltage Difference Transconductance Amplifier 使用电压差跨导放大器的积分器电路的勘误表

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/J.SSEL.2020.12.002

K. M. Santhoshini, Sarada Musala, Avireni Srinivasulu

引用次数: 1

Design and Optimization of Double Balanced Gilbert Cell Mixer in 130 nm CMOS Process 130 nm CMOS双平衡Gilbert Cell混频器的设计与优化

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.12.004

Dr. Satyanarayana R․V․S․, Subramanyam Avvaru

引用次数: 3

Nano-pillars metasurface modelled for perfect absorption at specific wavelengths in infrared spectral regime 纳米柱超表面模型的完美吸收在特定波长的红外光谱制度

Solid State Electronics Letters Pub Date : 2020-12-01 DOI: 10.1016/j.ssel.2020.11.002

Roxana Tomescu, Cristian Kusko, Dana Cristea, Ramona Calinoiu, Catalin Parvulescu

引用次数: 5