Fast and energy efficient full adder circuit using 14 CNFETs

With the increasing demand for faster, efficient and robust computational devices, the industrial research in circuit design deals with the challenges like size, power, efficiency and scalability. The designers have an array of choices to make use of different design approaches, material or technology to cater to these demands. In recent times, Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an improvised alternative for designing high-speed, low-power and cost-effective circuits. In this manuscript, 1-bit Full Adder circuit (1b-FA) using 14 CNFETs is being proposed in an effort to improve upon the aforesaid characteristics. The design being proposed is simulated with 32 nm CNFET technology at a supply voltage (V_DD) of +0.9V using Cadence Virtuoso CAD tool. The performance analysis of various existing full adder designs has been undertaken against proposed design in terms of power, delay and power-delay product (PDP). Parametric variations in CNFET diameter (D_CNT) and threshold voltage (V_th) was done for the analysis of output stability. Further, n-bit ripple carry adder (nb-RCA) for (n = 4, 8, 16, 32) was implemented using 1b-FA and compared with the existing nb-RCAs to analyze the performance and efficiency. Later, features like auto fault correction in outputs of 1b-FA were added.