{"title":"10nm通道长度n型无结变势垒纳米线晶体管的研究","authors":"Keng-Ming Liu, Sheng-Hong Liao","doi":"10.1016/j.ssel.2020.06.001","DOIUrl":null,"url":null,"abstract":"<div><p>In this paper we simulated and investigated the device characteristics of a novel device structure derived from the junctionless (JL) gate-all-around (GAA) nanowire (NW) transistor, variable barrier transistor (VBT). Basically, VBT is accomplished by the local constrictions at both ends of the channel region of the JL GAA NW transistor. The device simulation is performed based on the non-equilibrium Green's function (NEGF) approach provided by the 3D TCAD device simulator, Atlas. The simulation results suggest the JL VBT can have larger ON/OFF current ratio than that of the JL GAA NW transistor as long as the constriction (or barrier) is properly designed.</p></div>","PeriodicalId":101175,"journal":{"name":"Solid State Electronics Letters","volume":"2 ","pages":"Pages 44-48"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/j.ssel.2020.06.001","citationCount":"1","resultStr":"{\"title\":\"Investigation on 10-nm channel-length n-type junctionless variable barrier nanowire transistor\",\"authors\":\"Keng-Ming Liu, Sheng-Hong Liao\",\"doi\":\"10.1016/j.ssel.2020.06.001\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><p>In this paper we simulated and investigated the device characteristics of a novel device structure derived from the junctionless (JL) gate-all-around (GAA) nanowire (NW) transistor, variable barrier transistor (VBT). Basically, VBT is accomplished by the local constrictions at both ends of the channel region of the JL GAA NW transistor. The device simulation is performed based on the non-equilibrium Green's function (NEGF) approach provided by the 3D TCAD device simulator, Atlas. The simulation results suggest the JL VBT can have larger ON/OFF current ratio than that of the JL GAA NW transistor as long as the constriction (or barrier) is properly designed.</p></div>\",\"PeriodicalId\":101175,\"journal\":{\"name\":\"Solid State Electronics Letters\",\"volume\":\"2 \",\"pages\":\"Pages 44-48\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://sci-hub-pdf.com/10.1016/j.ssel.2020.06.001\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid State Electronics Letters\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S2589208820300156\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid State Electronics Letters","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2589208820300156","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Investigation on 10-nm channel-length n-type junctionless variable barrier nanowire transistor
In this paper we simulated and investigated the device characteristics of a novel device structure derived from the junctionless (JL) gate-all-around (GAA) nanowire (NW) transistor, variable barrier transistor (VBT). Basically, VBT is accomplished by the local constrictions at both ends of the channel region of the JL GAA NW transistor. The device simulation is performed based on the non-equilibrium Green's function (NEGF) approach provided by the 3D TCAD device simulator, Atlas. The simulation results suggest the JL VBT can have larger ON/OFF current ratio than that of the JL GAA NW transistor as long as the constriction (or barrier) is properly designed.
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