Memories - Materials, Devices, Circuits and Systems最新文献_第8页

Fatigue behavior of 3D stacked packaging structures under extreme thermal cycling condition 三维堆叠封装结构在极端热循环条件下的疲劳行为

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100032

Xin Xu , Yang Liu , Yahui Su , Cong Sun , Yuxiong Xue , Lina Ju , Shuye Zhang

{"title":"Fatigue behavior of 3D stacked packaging structures under extreme thermal cycling condition","authors":"Xin Xu , Yang Liu , Yahui Su , Cong Sun , Yuxiong Xue , Lina Ju , Shuye Zhang","doi":"10.1016/j.memori.2023.100032","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100032","url":null,"abstract":"<div><p>In deep space exploration environment, electronic devices face severe tests. C4 solder joints and TSV, as the weak links of the three-dimensional packaging structure, have a significant impact on the reliability of the packaging structure. This work focuses on the typical three-dimensional packaging structure and utilizes finite element software to analyze the influence of extreme thermal cycling on the fatigue life of packaging structure. The results show that under the extreme temperature range of -100<span><math><mo>∼</mo></math></span>120 °C, the maximum stress concentration of a typical 3D packaging structure occurs at the interface between the TSV and Si chip, and the TSV and C4 solder joints remote from the center bear greater stress and strain. The maximum stress of TSV appears at the end edge of TSV at the upper left corner. The maximum stress of the C4 welding spot appears on the second welding spot in the rightmost column. The most dangerous TSV fatigue life is 1.07 × 10<sup>7</sup> cycles calculated by combining the finite element simulation results with the Coffin Manson model. The life of the most dangerous C4 solder joint is 2892 cycles. C4 solder joint is the failure-sensitive location of the three-dimensional packaging structure under extreme ambient temperature, and optimization design is required in the subsequent work to improve its reliable life.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100032"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield 三门动态闪存（3G_DFM）设计对长空穴保持时间和鲁棒干扰屏蔽的影响

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100054

Koji Sakui, Yisuo Li, Masakazu Kakumu, Kenichi Kanazawa, Iwao Kunishima, Yoshihisa Iwata, Nozomu Harada

引用次数: 0

A subranging nonuniform sampling memristive neural network-based analog-to-digital converter 一种基于子范围非均匀采样忆阻神经网络的模数转换器

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100038

Hao You , Amirali Amirsoleimani , Jianxiong Xu , Mostafa Rahimi Azghadi , Roman Genov

{"title":"A subranging nonuniform sampling memristive neural network-based analog-to-digital converter","authors":"Hao You , Amirali Amirsoleimani , Jianxiong Xu , Mostafa Rahimi Azghadi , Roman Genov","doi":"10.1016/j.memori.2023.100038","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100038","url":null,"abstract":"<div><p>This work presents a novel 4-bit subranging nonuniform sampling (NUS) memristive neural network-based analog-to-digital converter (ADC) with improved performance trade-off among speed, power, area, and accuracy. The proposed design preserves the memristive neural network calibration and utilizes a trainable memristor weight to adapt to device mismatch and increase accuracy. Rather than conventional binary searching, we adopt quaternary searching in the ADC to realize subranging architecture’s coarse and fine bits determination. A level-crossing nonuniform sampling (NUS) is introduced to the proposed ADC to enhance the ENOB under the same resolutions, power, and area consumption. Area and power consumption are reduced through circuit sharing between different stages of bit determination. The proposed 4-bit ADC achieves a highest ENOB of 5.96 and 5.6 at cut-off frequency (128 <span><math><mi>MHz</mi></math></span>) with power consumption of 0.515 <span><math><mi>mW</mi></math></span> and a figure of merit (FoM) of 82.95 <span><math><mi>fJ/conv</mi></math></span>.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100038"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Flux-charge analysis and experimental verification of a parallel Memristor–Capacitor circuit 并联忆阻器-电容器电路的通量电荷分析与实验验证

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100043

M.A. Carrasco-Aguilar, F.E. Morales-López, C. Sánchez-López, Rocio Ochoa-Montiel

{"title":"Flux-charge analysis and experimental verification of a parallel Memristor–Capacitor circuit","authors":"M.A. Carrasco-Aguilar, F.E. Morales-López, C. Sánchez-López, Rocio Ochoa-Montiel","doi":"10.1016/j.memori.2023.100043","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100043","url":null,"abstract":"<div><p>In this article, the flux-charge analysis method is applied to obtain the theoretical response of the voltage generated in a parallel Memristor–Capacitor (M–C) circuit excited by an input pulse generator with a 100 kHz frequency, 5 V amplitude and a 50 ohms output impedance. The theoretical solution of the nonlinear ordinary differential equation that results when applying the method is reached by a numerical method. As a memristive circuit, a previously reported floating memristor emulator was used. The response obtained is compared with the experimental response, generating evidence that the applied analysis method yields an acceptable margin of error with regards to the experimental results obtained, contrasting with other similar reports, where the analyzes are based on theoretical memristive models, and show simulation results only. Summary, the paper would contribute to the analysis and experimental verification of the parallel M–C circuit subjected to a real switched exciting source, using a memristance equation established in an emulator that is different from the equations commonly used in the literature.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100043"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A review on computational storage devices and near memory computing for high performance applications 用于高性能应用的计算存储设备和近内存计算综述

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100051

Dina Fakhry , Mohamed Abdelsalam , M. Watheq El-Kharashi , Mona Safar

{"title":"A review on computational storage devices and near memory computing for high performance applications","authors":"Dina Fakhry , Mohamed Abdelsalam , M. Watheq El-Kharashi , Mona Safar","doi":"10.1016/j.memori.2023.100051","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100051","url":null,"abstract":"<div><p>The von Neumann bottleneck is imposed due to the explosion of data transfers and emerging data-intensive applications in heterogeneous system architectures. The conventional computation approach of transferring data to CPU is no longer suitable especially with the cost it imposes. Given the increasing storage capacities, moving extensive data volumes between storage and computation cannot scale up. Hence, high-performance data processing mechanisms are needed, which may be achieved by bringing computation closer to data. Gathering insights where data is stored helps deal with energy efficiency, low latency, as well as security. Storage bus bandwidth is also saved when only computation results are delivered to the host memory. Various applications, including database acceleration, machine learning, Artificial Intelligence (AI), offloading (compression/encryption/encoding) and others can perform better and become more scalable if the “move process to data” paradigm is applied. Embedding processing engines inside Solid-State Drives (SSDs), transforming them to Computational Storage Devices (CSDs), provides the needed data processing solution. In this paper, we review the prior art on Near Data Processing (NDP) with focus on In-Storage Computing (ISC), identifying main challenges and potential gaps for future research directions.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100051"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Realization of multi-mode universal shadow filter and its application as a frequency-hopping filter 多模通用阴影滤波器的实现及其作为跳频滤波器的应用

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100049

Divya Singh, Sajal K. Paul

引用次数: 0

Reconfigurable optoelectronic absorber based on nested nano disk-ribbon graphene Pattern in THz range 太赫兹范围内基于嵌套纳米盘带石墨烯图案的可重构光电子吸收器

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100039

Ilghar Rezaei , Ava Salmanpour , Toktam Aghaee

引用次数: 5

Improvement of memory performance of 3-D NAND flash memory with retrograde channel doping 反向沟道掺杂改善三维NAND闪存的存储性能

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100031

Deepika Gupta , Abhishek Kumar Upadhyay , Ankur Beohar , Santosh Kumar Vishvakarma

引用次数: 0

FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication FourierPIM：高吞吐量内存快速傅立叶变换和多项式乘法

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100034

Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky

{"title":"FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication","authors":"Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky","doi":"10.1016/j.memori.2023.100034","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100034","url":null,"abstract":"<div><p>The Discrete Fourier Transform (DFT) is essential for various applications ranging from signal processing to convolution and polynomial multiplication. The groundbreaking Fast Fourier Transform (FFT) algorithm reduces DFT time complexity from the naive <span><math><mrow><mi>O</mi><mrow><mo>(</mo><msup><mrow><mi>n</mi></mrow><mrow><mn>2</mn></mrow></msup><mo>)</mo></mrow></mrow></math></span> to <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mi>n</mi><mo>log</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span>, and recent works have sought further acceleration through parallel architectures such as GPUs. Unfortunately, accelerators such as GPUs cannot exploit their full computing capabilities since memory access becomes the bottleneck. Therefore, this paper accelerates the FFT algorithm using digital Processing-in-Memory (PIM) architectures that shift computation into the memory by exploiting physical devices capable of both storage and logic (e.g., memristors). We propose an <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mo>log</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span> in-memory FFT algorithm that can also be performed in parallel across multiple arrays for <em>high-throughput batched execution</em>, supporting both fixed-point and floating-point numbers. Through the convolution theorem, we extend this algorithm to <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mo>log</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span> polynomial multiplication – a fundamental task for applications such as cryptography. We evaluate FourierPIM on a publicly-available cycle-accurate simulator that verifies both correctness and performance, and demonstrate <span><math><mrow><mtext>5–15</mtext><mo>×</mo></mrow></math></span> throughput and <span><math><mrow><mtext>4–13</mtext><mo>×</mo></mrow></math></span> energy improvement over the NVIDIA cuFFT library on state-of-the-art GPUs for FFT and polynomial multiplication.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100034"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A survey on processing-in-memory techniques: Advances and challenges 记忆加工技术研究进展与挑战

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2022.100022

Kazi Asifuzzaman, Narasinga Rao Miniskar, Aaron R. Young, Frank Liu, Jeffrey S. Vetter

{"title":"A survey on processing-in-memory techniques: Advances and challenges","authors":"Kazi Asifuzzaman, Narasinga Rao Miniskar, Aaron R. Young, Frank Liu, Jeffrey S. Vetter","doi":"10.1016/j.memori.2022.100022","DOIUrl":"https://doi.org/10.1016/j.memori.2022.100022","url":null,"abstract":"<div><p>Processing-in-memory (PIM) techniques have gained much attention from computer architecture researchers, and significant research effort has been invested in exploring and developing such techniques. Increasing the research activity dedicated to improving PIM techniques will hopefully help deliver PIM’s promise to solve or significantly reduce memory access bottleneck problems for memory-intensive applications. We also believe it is imperative to track the advances made in PIM research to identify open challenges and enable the research community to make informed decisions and adjust future research directions. In this survey, we analyze recent studies that explored PIM techniques, summarize the advances made, compare recent PIM architectures, and identify target application domains and suitable memory technologies. We also discuss proposals that address unresolved issues of PIM designs (e.g., address translation/mapping of operands, workload analysis to identify application segments that can be accelerated with PIM, OS/runtime support, and coherency issues that must be resolved to incorporate PIM). We believe this work can serve as a useful reference for researchers exploring PIM techniques.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100022"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10