Memories - Materials, Devices, Circuits and Systems最新文献_第9页

Reconfigurable optoelectronic absorber based on nested nano disk-ribbon graphene Pattern in THz range 太赫兹范围内基于嵌套纳米盘带石墨烯图案的可重构光电子吸收器

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100039

Ilghar Rezaei , Ava Salmanpour , Toktam Aghaee

引用次数: 5

Improvement of memory performance of 3-D NAND flash memory with retrograde channel doping 反向沟道掺杂改善三维NAND闪存的存储性能

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100031

Deepika Gupta , Abhishek Kumar Upadhyay , Ankur Beohar , Santosh Kumar Vishvakarma

引用次数: 0

FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication FourierPIM：高吞吐量内存快速傅立叶变换和多项式乘法

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100034

Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky

{"title":"FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication","authors":"Orian Leitersdorf, Yahav Boneh, Gonen Gazit, Ronny Ronen, Shahar Kvatinsky","doi":"10.1016/j.memori.2023.100034","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100034","url":null,"abstract":"<div><p>The Discrete Fourier Transform (DFT) is essential for various applications ranging from signal processing to convolution and polynomial multiplication. The groundbreaking Fast Fourier Transform (FFT) algorithm reduces DFT time complexity from the naive <span><math><mrow><mi>O</mi><mrow><mo>(</mo><msup><mrow><mi>n</mi></mrow><mrow><mn>2</mn></mrow></msup><mo>)</mo></mrow></mrow></math></span> to <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mi>n</mi><mo>log</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span>, and recent works have sought further acceleration through parallel architectures such as GPUs. Unfortunately, accelerators such as GPUs cannot exploit their full computing capabilities since memory access becomes the bottleneck. Therefore, this paper accelerates the FFT algorithm using digital Processing-in-Memory (PIM) architectures that shift computation into the memory by exploiting physical devices capable of both storage and logic (e.g., memristors). We propose an <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mo>log</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span> in-memory FFT algorithm that can also be performed in parallel across multiple arrays for <em>high-throughput batched execution</em>, supporting both fixed-point and floating-point numbers. Through the convolution theorem, we extend this algorithm to <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mo>log</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span> polynomial multiplication – a fundamental task for applications such as cryptography. We evaluate FourierPIM on a publicly-available cycle-accurate simulator that verifies both correctness and performance, and demonstrate <span><math><mrow><mtext>5–15</mtext><mo>×</mo></mrow></math></span> throughput and <span><math><mrow><mtext>4–13</mtext><mo>×</mo></mrow></math></span> energy improvement over the NVIDIA cuFFT library on state-of-the-art GPUs for FFT and polynomial multiplication.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100034"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A survey on processing-in-memory techniques: Advances and challenges 记忆加工技术研究进展与挑战

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2022.100022

Kazi Asifuzzaman, Narasinga Rao Miniskar, Aaron R. Young, Frank Liu, Jeffrey S. Vetter

{"title":"A survey on processing-in-memory techniques: Advances and challenges","authors":"Kazi Asifuzzaman, Narasinga Rao Miniskar, Aaron R. Young, Frank Liu, Jeffrey S. Vetter","doi":"10.1016/j.memori.2022.100022","DOIUrl":"https://doi.org/10.1016/j.memori.2022.100022","url":null,"abstract":"<div><p>Processing-in-memory (PIM) techniques have gained much attention from computer architecture researchers, and significant research effort has been invested in exploring and developing such techniques. Increasing the research activity dedicated to improving PIM techniques will hopefully help deliver PIM’s promise to solve or significantly reduce memory access bottleneck problems for memory-intensive applications. We also believe it is imperative to track the advances made in PIM research to identify open challenges and enable the research community to make informed decisions and adjust future research directions. In this survey, we analyze recent studies that explored PIM techniques, summarize the advances made, compare recent PIM architectures, and identify target application domains and suitable memory technologies. We also discuss proposals that address unresolved issues of PIM designs (e.g., address translation/mapping of operands, workload analysis to identify application segments that can be accelerated with PIM, OS/runtime support, and coherency issues that must be resolved to incorporate PIM). We believe this work can serve as a useful reference for researchers exploring PIM techniques.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100022"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM Memories 降低电压自刷新（VRSR）优化DRAM存储器的节能

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100058

Diyanesh Chinnakkonda , Venkata Kalyan Tavva , M.B. Srinivas

{"title":"Voltage Reduced Self Refresh (VRSR) for optimized energy savings in DRAM Memories","authors":"Diyanesh Chinnakkonda , Venkata Kalyan Tavva , M.B. Srinivas","doi":"10.1016/j.memori.2023.100058","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100058","url":null,"abstract":"<div><p>Modern computing systems demand DRAMs with more capacity and bandwidth to keep pace with the onslaught of new data-intensive applications. Though DRAM scaling offers higher density devices to realize high memory capacity systems, energy consumption has become a key design limiter. This is owing to the fact that the memory sub-system continues to be responsible for a significant fraction of overall system energy. Self-refresh mode is one low power state that consumes the least DRAM energy, and this is an essential operation to avoid data loss. However, self-refresh energy also continues to grow with density scaling. This paper carries out a detailed study of reducing self-refresh energy by reducing the supply voltage. PARSEC benchmarks in Gem5 full-system mode are used to quantify the merit of self-refresh energy savings at reduced voltages for normal, reduced, and extended temperature ranges. The latency impacts of basic operations involved in self-refresh operation are evaluated using the 16 nm SPICE model. Possible limitations in extending the work to real hardware are also discussed. As a potential opportunity to motivate for future implementation, DRAM architectural changes, additional low power states and entry/exit flow to exercise reduced voltage operation in self-refresh mode are proposed. We present this new low power mode as Voltage Reduced Self-Refresh (VRSR) operation. Our simulation results show that there is a maximum of <span><math><mo>∼</mo></math></span>12.4% and an average of <span><math><mo>∼</mo></math></span>4% workload energy savings, with less than 0.7% performance loss across all benchmarks, for an aggressive voltage reduction of 150 mV.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100058"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient grouping approach for fault tolerant weight mapping in memristive crossbar array 忆阻纵横制阵列中容错权值映射的有效分组方法

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100045

Dev Narayan Yadav , Phrangboklang Lyngton Thangkhiew , Sandip Chakraborty , Indranil Sengupta

{"title":"Efficient grouping approach for fault tolerant weight mapping in memristive crossbar array","authors":"Dev Narayan Yadav , Phrangboklang Lyngton Thangkhiew , Sandip Chakraborty , Indranil Sengupta","doi":"10.1016/j.memori.2023.100045","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100045","url":null,"abstract":"<div><p>The ability of resistive memory (ReRAM) to naturally conduct vector–matrix multiplication (VMM), which is the primary operation carried out during the training and inference of neural networks, has caught the interest of researchers. The memristor crossbar is one of the desirable architectures to perform VMM because it offers various benefits over other memory technologies, including in-memory computing, low power, and high density. Direct downloading and chip-on-the-loop approaches are typically used to train ReRAM-based neural networks. In these methods, all weight computations are carried out by a host machine, and the computed weights are downloaded in the crossbar. It has been seen that the network does not deliver the same precision as promised by the host system once the weights have been downloaded. This is because crossbars contain a significant number of faulty memristors and suffer from cell resistance variations because of immature manufacturing technologies. As a result, a cell may not be able to take the exact weight values that the host system generates, and may lead to incorrect inferences. Existing techniques for fault-tolerant mapping either involve network retraining or employ a graph-matching strategy that comes with hardware, power, and latency overheads. In this paper, we propose a mapping method to tolerate the effect of defective memristors. In order to lessen the impact of faulty memristors, the mapping is done in a way that allows network weights to cover up faulty memristors. Further, this work prioritizes the different faults based on the frequency of occurrence. The mapping efficiency is found to increase significantly with low power, area and latency overheads in the proposed approach. Experimental analyses show considerable improvement as compared to state-of-the-art works.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100045"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Improved reliability single loop single feed 7T SRAM cell for biomedical applications 用于生物医学应用的提高可靠性的单环单馈7T SRAM单元

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100057

Ashish Panchal , Priyanka Sharma , Aastha Gupta , Vaibhav Neema , Nidhi Tiwari , Ravi Sindal

{"title":"Improved reliability single loop single feed 7T SRAM cell for biomedical applications","authors":"Ashish Panchal , Priyanka Sharma , Aastha Gupta , Vaibhav Neema , Nidhi Tiwari , Ravi Sindal","doi":"10.1016/j.memori.2023.100057","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100057","url":null,"abstract":"<div><p>Portable biomedical devices are born to reach a maximum number of people at an effective cost, and because of their small size and battery operation, the impact of portable medical devices is huge. For biomedical image processing devices, it is very important to store pixel information in embedded memory, because pixel values contain critical information about the image. For this critical information storage, most embedded memories consist of static random access memory (SRAM). SRAM, which stores critical information must have a high level of stability and reliability with low power dissipation. This paper proposes a single loop single-feed 7T (SLSF7T) SRAM cell that operates in the sub-threshold region (reducing the supply voltage to reduce power dissipation) and attains a high read static margin. To evaluate the read-and-write stability of the SRAM cell, the N-curve method is adopted in this work.</p><p>The proposed SLSF7T SRAM cell design offers several improvements over existing Biomedical Transmission Gate 8T (BT8T) and 9T SRAM cells. Specifically, the SLSF7T SRAM cell design shows an increase in static voltage noise margin (SVNM) by 75.86% and 75.34%, reduction in delay by 37.86% and 58.52%, and also offers less leakage power dissipation by 72% and 23.29% as compared to the BT8T and 9T cells, respectively. Along with the low power and high stability, the other most significant feature of the proposed work is its area efficiency because the proposed memory cell only consists of 7 transistors, it requires only 1.1X area overhead compared to the conventional 6T memory cell. The calculated performance matrix of the proposed cell is the highest among the considered SRAM cells for compression. The proposed cell operates in the sub-threshold region and achieves the best performance parameters for memory design for biomedical devices and applications at a 300 mV supply voltage.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100057"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Stress Issue of Vertical Connections in 3D Integration for High-Bandwidth Memory Applications 高带宽存储器应用三维集成中垂直连接的应力问题

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100024

Tzu-Heng Hung , Yu-Ming Pan , Kuan-Neng Chen

引用次数: 1

Exploiting switching properties of non-volatile memory chips for data security applications 利用非易失性存储芯片的开关特性实现数据安全应用

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100044

Supriya Chakraborty, Manan Suri

引用次数: 0

Fixed charges at the HfO2/SiO2 interface: Impact on the memory window of FeFET HfO2/SiO2界面的固定电荷：对FeFET存储窗口的影响

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-07-01 DOI: 10.1016/j.memori.2023.100050

Masud Rana Sk , Shubham Pande , Franz Müller , Yannick Raffel , Maximilian Lederer , Luca Pirro , Sven Beyer , Konrad Seidel , Thomas Kämpfe , Sourav De , Bhaswar Chakrabarti

引用次数: 0