Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Energy-efficient non-volatile latch using SOT-MTJ for enhanced logic and memory applications","authors":"Nikhil M.L. ,&nbsp;T.Y. Satheesha ,&nbsp;Shashidhara M. ,&nbsp;Abhishek Acharya","doi":"10.1016/j.memori.2025.100137","DOIUrl":"10.1016/j.memori.2025.100137","url":null,"abstract":"<div><div>This paper presents a pioneering self-SHE assisted Spin-Orbit Torque Magnetic Tunnel Junction (SOT-MTJ) design, meticulously crafted for enhancing logic-in-memory applications. A novel Non-Volatile (NV) latch based on SOT-MTJ technology is proposed, demonstrating superior energy efficiency and compactness. The proposed NV latch achieves a power dissipation of 18.87 <span><math><mi>μ</mi></math></span>W, energy consumption of 75.4 fJ, and a delay of 0.2 ns, setting a new benchmark in NV latch performance. When incorporated into a 1-bit NV full adder, the design achieves a power consumption of 6.55 <span><math><mi>μ</mi></math></span>W, a delay of 86.57 ps, and requires only 59 MOS + 1 MTJ, showcasing its compactness and efficiency compared to conventional designs. These advancements underline the proposed SOT-MTJ-based NV latch and full adder as pivotal components for energy-efficient, high-performance non-volatile logic circuits, paving the way for future innovations in LiM architectures.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"12 ","pages":"Article 100137"},"PeriodicalIF":0.0,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145765939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi armed bandit based resource allocation in Near Memory Processing architectures","authors":"Shubhang Pandey,&nbsp;T.G. Venkatesh","doi":"10.1016/j.memori.2025.100132","DOIUrl":"10.1016/j.memori.2025.100132","url":null,"abstract":"<div><div>Recent advances in 3D fabrication have allowed handling the memory bottlenecks for modern data-intensive applications by bringing the computation closer to the memory, enabling Near Memory Processing (NMP). Memory Centric Networks (MCN) are advanced memory architectures that use NMP architectures, where multiple stacks of the 3D memory units are equipped with simple processing cores, allowing numerous threads to execute concurrently. The performance of the NMP is crucially dependent upon the efficient task offloading and task-to-NMP allocation. Our work presents a multi-armed bandit (MAB) based approach in formulating an efficient resource allocation strategy for MCN. Most existing literature concentrates only on one application domain and optimizing only one metric, i.e., either execution time or power. However, our solution is more generic and can be applied to diverse application domains. In our approach, we deploy Upper Confidence Bound (UCB) policy to collect rewards and eventually use it for regret optimization. We study the following metrics-instructions per cycle, execution times, NMP core cache misses, packet latencies, and power consumption. Our study covers various applications from PARSEC and SPLASH2 benchmarks suite. The evaluation shows that the system’s performance improves by <span><math><mrow><mo>∼</mo><mn>11</mn><mtext>%</mtext></mrow></math></span> on average and an average reduction in total power consumption by <span><math><mrow><mo>∼</mo><mn>12</mn><mtext>%</mtext></mrow></math></span>.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"11 ","pages":"Article 100132"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144678812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical Unclonable Function (PUF) device based on single stage voltage amplifiers for secure signature generation in the Internet of Things","authors":"Marco Grossi,&nbsp;Martin Omaña","doi":"10.1016/j.memori.2025.100135","DOIUrl":"10.1016/j.memori.2025.100135","url":null,"abstract":"<div><div>Wireless sensor networks based on the Internet of Things (IoT) paradigm are of paramount importance to collect and share large amount of data in different fields of application. At the same time, cyberattacks represent a serious threat for the security of IoT systems and countermeasures have been proposed to mitigate the risks of cyberattacks in IoT systems.</div><div>Physical Unclonable Functions (PUF) are devices that exploit the random variations of the device parameters introduced during the manufacturing process to generate a secret key that can be considered virtually unclonable. PUF devices can be used, for instance, to generate a secure signature for device authentication or cryptographic algorithms.</div><div>In this paper, we present a PUF device that is based on the uncertainties due to transistors’ manufacturing parameters present in a single stage voltage amplifier. We present two different PUF implementations, one implemented by using bipolar junction transistors (BJTs) and the other implemented by using metal oxide semiconductor (MOS) transistors. We compare their performance by means of experimental measurements. The experimental results have shown that the best performance is achieved by the PUF based on BJT transistors, which features acceptable values of uniqueness (44.98 %), and uniformity (52.40 %), with very high values of steadiness and reliability to temperature and power supply fluctuations (all above 99.40 %). Instead, the PUF based on MOS transistors presents a lower steadiness and reliability than the PUF based on BJTs, but it can generate responses with higher number of bits, thus increasing security.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"11 ","pages":"Article 100135"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145265207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance investigation of 1T1R memory cell using GAA MBC-FET technology","authors":"Rinku Rani Das ,&nbsp;Devenderpal Singh ,&nbsp;Alex James","doi":"10.1016/j.memori.2025.100136","DOIUrl":"10.1016/j.memori.2025.100136","url":null,"abstract":"<div><div>The ultimate advancement beyond FinFET technology is the Gate-All-Around (GAA) Multi-Bridge-Channel FET (MBCFET) technology. GAA MBCFET features vertically stacked multiple channels, a departure from single-channel designs, thereby enhancing overall device efficiency. This study explores four configurations (C1, C2, C3, and C4) of GAA MBCFET, where various channel arrangements are investigated. The impact of these channels on DC, RF/analog performance is analyzed, revealing that the GAA MBCFET device with four thin channels (C4) exhibits robust resistance to short channel effects (SCE) parameters, such as threshold voltage variation, Subthreshold Swing (SS), and Drain-Induced Barrier Lowering (DIBL). Moreover, the GAA MBCFET demonstrates superior RF and analog performance attributes, offering promising prospects for the design of RFIC circuits. The 1T1R memory cell implementation using GAA MBC-FET technology has been analyzed to observe the DC, transient analysis. This research suggests that the future integration of GAA MBCFETs holds the potential for significant enhancements in device performance, encompassing improved power efficiency, higher speeds, and overall superior capabilities.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"11 ","pages":"Article 100136"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145519643","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simplifying activations with linear approximations in neural networks","authors":"Srinivas Rahul Sapireddy ,&nbsp;Kazi Asifuzzaman ,&nbsp;Rahman Mostafizur","doi":"10.1016/j.memori.2025.100134","DOIUrl":"10.1016/j.memori.2025.100134","url":null,"abstract":"<div><div>A key step in Neural Networks is activation. Among the different types of activation functions, sigmoid, tanh, and others involve the usage of exponents for calculation. From a hardware perspective, exponential implementation implies the usage of Taylor series or repeated methods involving many addition, multiplication, and division steps, and as a result are power-hungry and consume many clock cycles. We implement a piecewise linear approximation of the sigmoid function as a replacement for standard sigmoid activation libraries. This approach provides a practical alternative by leveraging piecewise segmentation, which simplifies hardware implementation and improves computational efficiency. In this paper, we detail piecewise functions that can be implemented using linear approximations and their implications for overall model accuracy and performance gain.</div><div>Our results show that for the DenseNet, ResNet, and GoogLeNet architectures, the piecewise linear approximation of the sigmoid function provides faster execution times compared to the standard TensorFlow sigmoid implementation while maintaining comparable accuracy. Specifically, for MNIST with DenseNet, accuracy reaches 99.91% (Piecewise) vs. 99.97% (Base) with up to 1.31<span><math><mo>×</mo></math></span> speedup in execution time. For CIFAR-10 with DenseNet, accuracy improves to 98.97% (Piecewise) vs. 99.40% (Base) while achieving 1.24<span><math><mo>×</mo></math></span> faster execution. Similarly, for CIFAR-100 with DenseNet, the accuracy is 97.93% (Piecewise) vs. 98.39% (Base), with a 1.18<span><math><mo>×</mo></math></span> execution time reduction. These results confirm the proposed method’s capability to efficiently process large-scale datasets and computationally demanding tasks, offering a practical means to accelerate deep learning models, including LSTMs, without compromising accuracy.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"11 ","pages":"Article 100134"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145319905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Role of electrode materials in resistive switching mechanisms of oxide-based memristors for enhanced neuromorphic computing: A comprehensive study","authors":"Armin Gooran-Shoorakchaly,&nbsp;Sarah Sharif,&nbsp;Yaser M. Banad","doi":"10.1016/j.memori.2025.100133","DOIUrl":"10.1016/j.memori.2025.100133","url":null,"abstract":"<div><div>This study extends the state-of-the-art TaOx-based memristors by explicitly coupling electrode-dependent thermal conductivity to the electrical-thermal solver and by treating drift, diffusion, and Soret flux on equal footing. By examining titanium (Ti), palladium (Pd), and tungsten (W) electrodes, conductive filament (CF) dynamics is studied, particularly the role of thermal and electrical properties in governing oxygen vacancy migration. The enriched model reveals that Ti's low thermal conductivity (21.9 W/m·K) lowers the forming voltage to −1.72 V and boosts the peak diffusion flux to 5.4 A/cm², whereas W's high thermal conductivity (174 W/m·K) suppresses filament growth, requiring −2.01 V. This is the first quantitative decomposition of the three vacancy-transport mechanisms under realistic Joule-heating conditions, enabling direct correlation between electrode choice and device variability. Our systematic analysis of drift, diffusion, and Soret flux mechanisms provides deeper insight into CF formation, stability, and device reliability. The insight translates into markedly tighter resistance distributions for Ti devices (σ/μ = 0.011 in LRS) and promising 10,000-s retention at 150 °C, pointing toward electrode-engineered RRAM for reliable neuromorphic computing. These findings underscore how careful electrode material selection can significantly enhance RRAM performance, reliability, and scalability, thereby presenting a promising device platform for neuromorphic and in-memory computing applications.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"11 ","pages":"Article 100133"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144489678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Counter-based CMOS QCWM demodulator for wide frequency range WPT biohealth applications","authors":"Mohd K. Zulkalnain,&nbsp;Adel Barakat,&nbsp;Naqeeb Ullah,&nbsp;Haruichi Kanaya,&nbsp;Ramesh K. Pokharel","doi":"10.1016/j.memori.2025.100128","DOIUrl":"10.1016/j.memori.2025.100128","url":null,"abstract":"<div><div>In this paper, a CMOS QCWM demodulator was designed to achieve a wide carrier frequency range to cater for a variety of applications. Previous designs utilize a pulse to sawtooth peak (PW2SP) converter and a comparator that necessitates a reference voltage, causing the frequency range to be limited, due to the current starved nature of the PW2SP circuit. To address this issue, a modified PW2SP employing a programmable current mirror with a 3-bit counter was proposed to provide current programmability and eliminate the use of a voltage reference. The proposed QCWM demodulator was designed and fabricated on 180 nm CMOS technology. The current programmability allows the QCWM demodulator to reach data rate of 400Kb/s to 8Mb/s, when the carrier frequency is varied from 1 MHz to 20 MHz. The design consumes 209 <span><math><mi>μ</mi></math></span>W at 20 MHz carrier frequency from a 1.4 V supply voltage with an energy consumption of 26.13 pJ/bit.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"10 ","pages":"Article 100128"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143682017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of an analog topology for a multi-layer neuronal network","authors":"Luã da Porciuncula Estrela ,&nbsp;Marlon Soares Sigales ,&nbsp;Elmer A. Gamboa Peñaloza ,&nbsp;Marcelo Lemos Rossi ,&nbsp;Mateus Beck Fonseca","doi":"10.1016/j.memori.2025.100125","DOIUrl":"10.1016/j.memori.2025.100125","url":null,"abstract":"<div><div>This paper presents a novel approach to implementing artificial neural networks (ANNs) using analog circuits with counter circuits for storing and updating the weights and biases. The counter circuits, which are sequential logic circuits, provide a more precise and stable method for storing and updating the network parameters, compared to memristors. The paper also discusses the design of a multiplier circuit and a hyperbolic function activation circuit used in the neural network. The neural network model based on the XNOR logic function was simulated using a simulation program with integrated circuit emphasis (SPICE), demonstrating its learning capability as the error decreased for each epoch of training. The proposed methodology offers significant advantages for neuromorphic computing, especially in the domain of Internet of Things (IoT), where near-sensor data analysis and edge computation are essential.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100125"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications","authors":"Venkata Sudhakar Chowdam ,&nbsp;Suresh Babu Potladurty ,&nbsp;Prasad Reddy karipireddy","doi":"10.1016/j.memori.2025.100123","DOIUrl":"10.1016/j.memori.2025.100123","url":null,"abstract":"<div><div>The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100123"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of generic vedic ALU using reversible logic","authors":"Kanchan S. Tiwari","doi":"10.1016/j.memori.2025.100121","DOIUrl":"10.1016/j.memori.2025.100121","url":null,"abstract":"<div><div>This paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to derive efficient computational methods, and reversible logic is harnessed to achieve minimal power dissipation and reduced heat generation in the ALU. The proposed ALU architecture is optimized to perform fundamental arithmetic operations: addition, subtraction, multiplication, and division; as well as bitwise logical operations: AND, OR, and XOR. Vedic mathematics techniques contribute to the reduction of critical paths and garbage outputs, enhancing the overall performance of the ALU. The design is synthesized and implemented on a device Xc7a35tcpg236 belonging to Artix-7 family of FPGA, and power consumption is evaluated and compared with conventional ALU designs. Performance parameters, including power consumption and delay, were benchmarked against existing designs. The designed ALU operates at a clock frequency of 408.197 MHz, featuring a maximum combinational path delay of 4.65 ns with input voltage of 1 V. Notable is its power efficiency, which consumes a mere 42 mW, as opposed to the conventional ALU with a power consumption of 73 mW. The Vinculum based logic of reducing bigger number to smaller ones thereby simplifying calculations is also added in the design. Incorporating Vedic reversible logic with vinculum in FPGA design introduces a novel approach leveraging parallelism and pipelining for enhanced efficiency and performance. Furthermore, the FPGA-based implementation showcases the scalability of the design for higher bit-width ALUs, highlighting its potential for integration into complex digital systems. The proposed Generic low-power Vedic ALU using reversible logic opens up new opportunities for energy-efficient computing applications, such as portable devices, embedded systems, and Internet of Things (IoT) devices. The fusion of Vedic mathematics with reversible logic offers a novel approach to design efficient ALUs, contributing to the advancement of low-power and high-performance digital circuitry.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100121"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}