Memories - Materials, Devices, Circuits and Systems最新文献

Role of electrode materials in resistive switching mechanisms of oxide-based memristors for enhanced neuromorphic computing: A comprehensive study 电极材料在增强神经形态计算的氧化基忆阻器电阻开关机制中的作用：一项综合研究

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-06-20 DOI: 10.1016/j.memori.2025.100133

Armin Gooran-Shoorakchaly, Sarah Sharif, Yaser M. Banad

{"title":"Role of electrode materials in resistive switching mechanisms of oxide-based memristors for enhanced neuromorphic computing: A comprehensive study","authors":"Armin Gooran-Shoorakchaly, Sarah Sharif, Yaser M. Banad","doi":"10.1016/j.memori.2025.100133","DOIUrl":"10.1016/j.memori.2025.100133","url":null,"abstract":"<div><div>This study extends the state-of-the-art TaOx-based memristors by explicitly coupling electrode-dependent thermal conductivity to the electrical-thermal solver and by treating drift, diffusion, and Soret flux on equal footing. By examining titanium (Ti), palladium (Pd), and tungsten (W) electrodes, conductive filament (CF) dynamics is studied, particularly the role of thermal and electrical properties in governing oxygen vacancy migration. The enriched model reveals that Ti's low thermal conductivity (21.9 W/m·K) lowers the forming voltage to −1.72 V and boosts the peak diffusion flux to 5.4 A/cm<sup>2</sup>, whereas W's high thermal conductivity (174 W/m·K) suppresses filament growth, requiring −2.01 V. This is the first quantitative decomposition of the three vacancy-transport mechanisms under realistic Joule-heating conditions, enabling direct correlation between electrode choice and device variability. Our systematic analysis of drift, diffusion, and Soret flux mechanisms provides deeper insight into CF formation, stability, and device reliability. The insight translates into markedly tighter resistance distributions for Ti devices (σ/μ = 0.011 in LRS) and promising 10,000-s retention at 150 °C, pointing toward electrode-engineered RRAM for reliable neuromorphic computing. These findings underscore how careful electrode material selection can significantly enhance RRAM performance, reliability, and scalability, thereby presenting a promising device platform for neuromorphic and in-memory computing applications.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"11 ","pages":"Article 100133"},"PeriodicalIF":0.0,"publicationDate":"2025-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144489678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implications of memory embedding and hierarchy on the performance of MAVeC AI accelerators 记忆嵌入和层次结构对MAVeC人工智能加速器性能的影响

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-04-01 DOI: 10.1016/j.memori.2025.100131

Md Rownak Hossain Chowdhury, Mostafizur Rahman

{"title":"Implications of memory embedding and hierarchy on the performance of MAVeC AI accelerators","authors":"Md Rownak Hossain Chowdhury, Mostafizur Rahman","doi":"10.1016/j.memori.2025.100131","DOIUrl":"10.1016/j.memori.2025.100131","url":null,"abstract":"<div><div>Memory organization is essential for any AI (Artificial Intelligence) processor, as memory mapped I/O dictates the system's overall throughput. Regardless of how fast or how many parallel processing units are integrated into the processor, the performance will ultimately suffer when data transfer rates fail to match processing capabilities. Therefore, the efficacy of data orchestration within the memory hierarchy is a foundational aspect in benchmarking the performance of any AI accelerator. In this work, we investigate memory organization for a messaging-based vector processing Unit (MAVeC), where data routes across computation units to enable adaptive programmability at runtime. MAVeC features a hierarchical on-chip memory structure of less than 100 MB to minimize data movement, enhance locality, and maximize parallelism. Complementing this, we develop an end-to-end data orchestration methodology to manage data flow within the memory hierarchy. To evaluate the overall performance incorporating memory, we detail our extensive benchmarking results across diverse parameters, including PCIe (Peripheral Component Interconnect Express) configurations, available hardware resources, operating frequencies, and off-chip memory bandwidth. The MAVeC achieves a notable throughput of 95.39K inferences per second for Alex Net, operating at a 1 GHz frequency with 64 tiles and 32-bit precision, using PCIe 6.0 × 16 and HBM4 off-chip memory. In TSMC 28 nm technology node the estimated area for the MAVeC core is approximately 346 mm<sup>2</sup>. These results underscore the potential of the proposed memory hierarchy for the MAVeC accelerator, positioning it as a promising solution for future AI applications.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"10 ","pages":"Article 100131"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144261298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Recent advancements and progress in development of ferroelectric field effect transistor: A review 铁电场效应晶体管的研究进展

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-04-01 DOI: 10.1016/j.memori.2025.100130

Mandeep Singh, Nakkina Sai Teja, Tarun Chaudhary, Balwinder Raj

{"title":"Recent advancements and progress in development of ferroelectric field effect transistor: A review","authors":"Mandeep Singh, Nakkina Sai Teja, Tarun Chaudhary, Balwinder Raj","doi":"10.1016/j.memori.2025.100130","DOIUrl":"10.1016/j.memori.2025.100130","url":null,"abstract":"<div><div>The robust application of ferroelectric materials in various disciplines has resulted in the development of significantly more accurate and potent FeFETs, which have the potential to deliver more promising non-volatile memory and synaptic devices than traditional ones. The present study illustrates the fundamental concepts, operation, and construction of FeFETs and presents a methodology to determine suitable ferroelectric materials, the make-up of gate stacks, and the advantages that are necessary for an efficient and commercial FeFET. Among various ferroelectric-based FETs, the HfO<sub>2</sub>-based FeEFT has exhibited much more potential and huge advantages such as thin profiles, high polarisation, data retention, and endurance, which have been thoroughly explored in the present study. This paper discusses the contemporary challenges in device design by focusing primarily on the performance parameters such as CMOS compatibility of ferroelectric materials, gate leakage current, depolarisation fields, and a few other factors. Considering these factors will ultimately influence the critical concerns associated with devising design and practical limitations.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"10 ","pages":"Article 100130"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Counter-based CMOS QCWM demodulator for wide frequency range WPT biohealth applications 宽频率范围WPT生物保健应用的基于计数器的CMOS QCWM解调器

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-03-18 DOI: 10.1016/j.memori.2025.100128

Mohd K. Zulkalnain, Adel Barakat, Naqeeb Ullah, Haruichi Kanaya, Ramesh K. Pokharel

引用次数: 0

Design an energy efficient ternary parallel prefix carry/sum propagate adders using 32-nm CNTFET 利用32nm CNTFET设计一种节能的三元并行前缀进位/和传播加法器

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-03-12 DOI: 10.1016/j.memori.2025.100129

Sudha Vani Yamani , H.K. Raghu Vamsi Kudulla , B.V.R.S. Ganesh , D. Sushma , Ch Manasa , Satti Harichandra Prasad

{"title":"Design an energy efficient ternary parallel prefix carry/sum propagate adders using 32-nm CNTFET","authors":"Sudha Vani Yamani , H.K. Raghu Vamsi Kudulla , B.V.R.S. Ganesh , D. Sushma , Ch Manasa , Satti Harichandra Prasad","doi":"10.1016/j.memori.2025.100129","DOIUrl":"10.1016/j.memori.2025.100129","url":null,"abstract":"<div><div>Every digital computer system utilizes binary adders. However, researchers have focused on ternary logic to reduce power consumption in digital systems. To implement a ternary logic circuit, Carbon Nano Tube Field Effect Transistors (CNTFETs) have been employed, as the threshold voltage (V<sub>th</sub>) of CNTFETs. Fundamentally, the carry look-ahead adders follow the parallel prefix carry propagation. In the parallel prefix adders, this propagates the carry/sum bits. The traditional Carry Propagate Adders (CPA) generate carry bits and propagate them. Their results show carry bit propagation needs time and extra circuits for carry generation, which occupies more chip area than Sum Propagation Adders (SPA). Specifically, this work explored the use of parallel prefix ternary sum/carry propagation adders with a proposed carry propagator block, which is a kind of multi-valued logic (MVL). This work utilized 32 nm CNTFETs to build the circuits. To evaluate the performance, simulations were conducted using Cadence Virtuoso Software for both the Ternary Carry Propagate Adder (TCPA) and the Ternary Sum Propagate Adder (TSPA). The results demonstrated that the 8-bit Kogge Stone TSPA exhibited a remarkable 37.3 % reduction in power consumption compared to the TCPA. Additionally, the 8-bit Kogge Stone TSPA also demonstrated a notable 45 % reduction in delay compared to the TCPA.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"10 ","pages":"Article 100129"},"PeriodicalIF":0.0,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of an analog topology for a multi-layer neuronal network 多层神经网络模拟拓扑的发展

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-02-11 DOI: 10.1016/j.memori.2025.100125

Luã da Porciuncula Estrela , Marlon Soares Sigales , Elmer A. Gamboa Peñaloza , Marcelo Lemos Rossi , Mateus Beck Fonseca

引用次数: 0

A graphene-based toxic detection approach 一种基于石墨烯的毒性检测方法

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-02-11 DOI: 10.1016/j.memori.2025.100127

Amir Ali Mohammad Khani , Alireza Barati Haghverdi , Ilghar Rezaei , Farzane Soleimani Rudi , Toktam Aghaee

{"title":"A graphene-based toxic detection approach","authors":"Amir Ali Mohammad Khani , Alireza Barati Haghverdi , Ilghar Rezaei , Farzane Soleimani Rudi , Toktam Aghaee","doi":"10.1016/j.memori.2025.100127","DOIUrl":"10.1016/j.memori.2025.100127","url":null,"abstract":"<div><div>Periodic arrays of graphene disks are leveraged to form a toxic gas detector. The operational frequency range is the THz gap. The idea stems from the middle air gap which is surrounded by graphene-spacer layers while a fully reflecting metallic surface is placed underneath. The change in the refractive index of the air gap due to the presence of some toxic gases leads to absorption deviations. Interpreting the known deviations can define a detection protocol in the THz spectrum. This work proposes a three-layer wave absorber based on the graphene patterns, TOPAS spacer, and the golden surface. Each component is modeled by the passive circuit element and the total impedance of the structure is calculated. Additionally, the impedance matching concept is investigated to predict absorption response. Furthermore, full-wave simulation is performed to compare with the circuit model approach. Based on the simulation results, a multi-band absorption response experiences considerable frequency shifts when exposed to some toxic gases including SO<sub>2</sub>, N<sub>2</sub>, NO<sub>2</sub>, O<sub>3,</sub> and CO. More importantly, the capability of being tuned via external chemical potential makes the proposed absorber an ideal basic building block for healthcare-based optical systems.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100127"},"PeriodicalIF":0.0,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143429438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Optimization of deep learning algorithms for large digital data processing using evolutionary neural networks 基于进化神经网络的大型数字数据处理深度学习算法优化

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-02-07 DOI: 10.1016/j.memori.2025.100126

Mohammadreza Nehzati

引用次数: 0

The application of organic materials used in IC advanced packaging:A review 有机材料在集成电路先进封装中的应用综述

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-01-20 DOI: 10.1016/j.memori.2025.100124

Liu Jikang

引用次数: 0

Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications 基于时钟门控的容错近似乘法器设计与评价

Memories - Materials, Devices, Circuits and Systems Pub Date : 2025-01-12 DOI: 10.1016/j.memori.2025.100123

Venkata Sudhakar Chowdam , Suresh Babu Potladurty , Prasad Reddy karipireddy

{"title":"Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications","authors":"Venkata Sudhakar Chowdam , Suresh Babu Potladurty , Prasad Reddy karipireddy","doi":"10.1016/j.memori.2025.100123","DOIUrl":"10.1016/j.memori.2025.100123","url":null,"abstract":"<div><div>The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100123"},"PeriodicalIF":0.0,"publicationDate":"2025-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0