Design an energy efficient ternary parallel prefix carry/sum propagate adders using 32-nm CNTFET

Every digital computer system utilizes binary adders. However, researchers have focused on ternary logic to reduce power consumption in digital systems. To implement a ternary logic circuit, Carbon Nano Tube Field Effect Transistors (CNTFETs) have been employed, as the threshold voltage (V_th) of CNTFETs. Fundamentally, the carry look-ahead adders follow the parallel prefix carry propagation. In the parallel prefix adders, this propagates the carry/sum bits. The traditional Carry Propagate Adders (CPA) generate carry bits and propagate them. Their results show carry bit propagation needs time and extra circuits for carry generation, which occupies more chip area than Sum Propagation Adders (SPA). Specifically, this work explored the use of parallel prefix ternary sum/carry propagation adders with a proposed carry propagator block, which is a kind of multi-valued logic (MVL). This work utilized 32 nm CNTFETs to build the circuits. To evaluate the performance, simulations were conducted using Cadence Virtuoso Software for both the Ternary Carry Propagate Adder (TCPA) and the Ternary Sum Propagate Adder (TSPA). The results demonstrated that the 8-bit Kogge Stone TSPA exhibited a remarkable 37.3 % reduction in power consumption compared to the TCPA. Additionally, the 8-bit Kogge Stone TSPA also demonstrated a notable 45 % reduction in delay compared to the TCPA.