Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Design of generic vedic ALU using reversible logic","authors":"Kanchan S. Tiwari","doi":"10.1016/j.memori.2025.100121","DOIUrl":"10.1016/j.memori.2025.100121","url":null,"abstract":"<div><div>This paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to derive efficient computational methods, and reversible logic is harnessed to achieve minimal power dissipation and reduced heat generation in the ALU. The proposed ALU architecture is optimized to perform fundamental arithmetic operations: addition, subtraction, multiplication, and division; as well as bitwise logical operations: AND, OR, and XOR. Vedic mathematics techniques contribute to the reduction of critical paths and garbage outputs, enhancing the overall performance of the ALU. The design is synthesized and implemented on a device Xc7a35tcpg236 belonging to Artix-7 family of FPGA, and power consumption is evaluated and compared with conventional ALU designs. Performance parameters, including power consumption and delay, were benchmarked against existing designs. The designed ALU operates at a clock frequency of 408.197 MHz, featuring a maximum combinational path delay of 4.65 ns with input voltage of 1 V. Notable is its power efficiency, which consumes a mere 42 mW, as opposed to the conventional ALU with a power consumption of 73 mW. The Vinculum based logic of reducing bigger number to smaller ones thereby simplifying calculations is also added in the design. Incorporating Vedic reversible logic with vinculum in FPGA design introduces a novel approach leveraging parallelism and pipelining for enhanced efficiency and performance. Furthermore, the FPGA-based implementation showcases the scalability of the design for higher bit-width ALUs, highlighting its potential for integration into complex digital systems. The proposed Generic low-power Vedic ALU using reversible logic opens up new opportunities for energy-efficient computing applications, such as portable devices, embedded systems, and Internet of Things (IoT) devices. The fusion of Vedic mathematics with reversible logic offers a novel approach to design efficient ALUs, contributing to the advancement of low-power and high-performance digital circuitry.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100121"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance memristor device from solution processed MnO2 nanowires: Tuning of resistive switching from analog to digital and underlying mechanism","authors":"Rajkumar Mandal,&nbsp;Arka Mandal,&nbsp;Nayan Pandit,&nbsp;Rajib Nath,&nbsp;Biswanath Mukherjee","doi":"10.1016/j.memori.2024.100120","DOIUrl":"10.1016/j.memori.2024.100120","url":null,"abstract":"<div><div>This study reports the synthesis of manganese dioxide (MnO₂) nanowires via the hydrothermal method and the fabrication of high-performance memristor devices using solution-processed MnO₂ nanowires. Microstructural characterizations, <em>viz</em>, XRD, SEM, EDAX and XPS of synthesized sample revealed highly crystalline structures of MnO₂ nanowires. As synthesized MnO₂ nanowires, mixed in different weight percentages with poly(methyl methacrylate) (PMMA) solution were deposited on Al electrode to form thin film memristor devices. Resistive switching with both analog and digital behaviors have been realized in Al/MnO₂-PMMA/Al device by controlling the weight percentage (wt %) of MnO₂ in the composite. When the MnO₂ wt % in the composite was low (PMMA: MnO₂ = 1:1), the device exhibited analog type switching, while, the higher concentration of MnO₂ produced digital types of switching. The On/Off current ratio of the device increased gradually with increase in MnO₂ wt %, reaching the highest switching ratio, <em>ca.</em> 10⁶ and excellent endurance (&gt;10⁴ s) for PMMA:MnO₂ = 1:8. Temperature dependent charge transport behavior and impedance spectroscopy was further carried out to explain the underlying resistive switching mechanism of the device.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100120"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implications of memory embedding and hierarchy on the performance of MAVeC AI accelerators","authors":"Md Rownak Hossain Chowdhury,&nbsp;Mostafizur Rahman","doi":"10.1016/j.memori.2025.100131","DOIUrl":"10.1016/j.memori.2025.100131","url":null,"abstract":"<div><div>Memory organization is essential for any AI (Artificial Intelligence) processor, as memory mapped I/O dictates the system's overall throughput. Regardless of how fast or how many parallel processing units are integrated into the processor, the performance will ultimately suffer when data transfer rates fail to match processing capabilities. Therefore, the efficacy of data orchestration within the memory hierarchy is a foundational aspect in benchmarking the performance of any AI accelerator. In this work, we investigate memory organization for a messaging-based vector processing Unit (MAVeC), where data routes across computation units to enable adaptive programmability at runtime. MAVeC features a hierarchical on-chip memory structure of less than 100 MB to minimize data movement, enhance locality, and maximize parallelism. Complementing this, we develop an end-to-end data orchestration methodology to manage data flow within the memory hierarchy. To evaluate the overall performance incorporating memory, we detail our extensive benchmarking results across diverse parameters, including PCIe (Peripheral Component Interconnect Express) configurations, available hardware resources, operating frequencies, and off-chip memory bandwidth. The MAVeC achieves a notable throughput of 95.39K inferences per second for Alex Net, operating at a 1 GHz frequency with 64 tiles and 32-bit precision, using PCIe 6.0 × 16 and HBM4 off-chip memory. In TSMC 28 nm technology node the estimated area for the MAVeC core is approximately 346 mm². These results underscore the potential of the proposed memory hierarchy for the MAVeC accelerator, positioning it as a promising solution for future AI applications.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"10 ","pages":"Article 100131"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144261298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compensation of active filter using p-q theory in photovoltaic systems","authors":"Farzane Soleimani Rudi,&nbsp;Mohammad Naser Hashemnia","doi":"10.1016/j.memori.2025.100122","DOIUrl":"10.1016/j.memori.2025.100122","url":null,"abstract":"<div><div>This work proposes an active shunt filter design for grid-connected solar systems, utilizing the p-q instantaneous power theory technique to minimize grid harmonics and reduce reactive power. As a result, the total harmonic distortion (THD) is decreased, and the power quality of the network is improved. To optimize the efficiency of solar panels and generate the switching control signal of the boost converter, the Perturb and Observe (P&amp;O) method and Pulse Width Modulation (PWM) technique are employed, respectively. The active shunt filter extracts the harmonic components of the load current using the p-q theory, which serves as a reference signal for compensation. A hysteresis method is used to control the filter current and produce the pulses for the filter switches. The designed filter reduces the harmonic distortion in the load current to approximately 29.91%. A comparison between the harmonic reference signal and the injected filter current to the three-phase grid confirms the correctness of the design. Moreover, the sinusoidal waveform of the three-phase grid currents demonstrates the effectiveness of the proposed controller. Simulation results in MATLAB validate the proposed filter, with the network current THD reduced to less than 5%, confirming the efficacy of the design.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100122"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A graphene-based toxic detection approach","authors":"Amir Ali Mohammad Khani ,&nbsp;Alireza Barati Haghverdi ,&nbsp;Ilghar Rezaei ,&nbsp;Farzane Soleimani Rudi ,&nbsp;Toktam Aghaee","doi":"10.1016/j.memori.2025.100127","DOIUrl":"10.1016/j.memori.2025.100127","url":null,"abstract":"<div><div>Periodic arrays of graphene disks are leveraged to form a toxic gas detector. The operational frequency range is the THz gap. The idea stems from the middle air gap which is surrounded by graphene-spacer layers while a fully reflecting metallic surface is placed underneath. The change in the refractive index of the air gap due to the presence of some toxic gases leads to absorption deviations. Interpreting the known deviations can define a detection protocol in the THz spectrum. This work proposes a three-layer wave absorber based on the graphene patterns, TOPAS spacer, and the golden surface. Each component is modeled by the passive circuit element and the total impedance of the structure is calculated. Additionally, the impedance matching concept is investigated to predict absorption response. Furthermore, full-wave simulation is performed to compare with the circuit model approach. Based on the simulation results, a multi-band absorption response experiences considerable frequency shifts when exposed to some toxic gases including SO₂, N₂, NO₂, O_3, and CO. More importantly, the capability of being tuned via external chemical potential makes the proposed absorber an ideal basic building block for healthcare-based optical systems.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100127"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143429438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The application of organic materials used in IC advanced packaging:A review","authors":"Liu Jikang","doi":"10.1016/j.memori.2025.100124","DOIUrl":"10.1016/j.memori.2025.100124","url":null,"abstract":"<div><div>With the development of advanced technologies, the importance of semiconductor packaging has been further highlighted. To meet the increasing complexity and performance requirements of semiconductor devices, many integrated circuit (IC) advanced packaging technologies have been developed, which including flip chip (FC), bumping, fan-in wafer level packaging (FIWLP), fan-out wafer level packaging (FOWLP), 2.5D packaging (interposer), CMOS image sensor through silicon via (CIS-TSV), fan-out panel level packaging (FOPLP) and so on. During the manufacturing process of those IC advanced packaging technologies, many organic materials including photoresist (PR), photosensitive polyimide (PSPI), underfill, epoxy molding compound (EMC), temporary bonding adhesive, high temperature bonding adhesive, dry film and printing ink have been applied. In this paper, we described the application of organic materials including PR, PSPI, underfill, EMC, temporary bonding adhesive, high temperature bonding adhesive, dry film and printing ink used in the IC advanced packaging.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100124"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design an energy efficient ternary parallel prefix carry/sum propagate adders using 32-nm CNTFET","authors":"Sudha Vani Yamani ,&nbsp;H.K. Raghu Vamsi Kudulla ,&nbsp;B.V.R.S. Ganesh ,&nbsp;D. Sushma ,&nbsp;Ch Manasa ,&nbsp;Satti Harichandra Prasad","doi":"10.1016/j.memori.2025.100129","DOIUrl":"10.1016/j.memori.2025.100129","url":null,"abstract":"<div><div>Every digital computer system utilizes binary adders. However, researchers have focused on ternary logic to reduce power consumption in digital systems. To implement a ternary logic circuit, Carbon Nano Tube Field Effect Transistors (CNTFETs) have been employed, as the threshold voltage (V_th) of CNTFETs. Fundamentally, the carry look-ahead adders follow the parallel prefix carry propagation. In the parallel prefix adders, this propagates the carry/sum bits. The traditional Carry Propagate Adders (CPA) generate carry bits and propagate them. Their results show carry bit propagation needs time and extra circuits for carry generation, which occupies more chip area than Sum Propagation Adders (SPA). Specifically, this work explored the use of parallel prefix ternary sum/carry propagation adders with a proposed carry propagator block, which is a kind of multi-valued logic (MVL). This work utilized 32 nm CNTFETs to build the circuits. To evaluate the performance, simulations were conducted using Cadence Virtuoso Software for both the Ternary Carry Propagate Adder (TCPA) and the Ternary Sum Propagate Adder (TSPA). The results demonstrated that the 8-bit Kogge Stone TSPA exhibited a remarkable 37.3 % reduction in power consumption compared to the TCPA. Additionally, the 8-bit Kogge Stone TSPA also demonstrated a notable 45 % reduction in delay compared to the TCPA.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"10 ","pages":"Article 100129"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of deep learning algorithms for large digital data processing using evolutionary neural networks","authors":"Mohammadreza Nehzati","doi":"10.1016/j.memori.2025.100126","DOIUrl":"10.1016/j.memori.2025.100126","url":null,"abstract":"<div><div>This paper introduces a unique method for boosting the efficiency of deep learning algorithms in processing large amounts of virtual facts. This approach leverages evolutionary neural networks, integrating deep mastering algorithms with evolutionary algorithms to enhance the overall performance of convolutional neural networks (CNNs) and recurrent neural networks (RNNs). The proposed optimization technique employs evolutionary operators such as natural choice, version aggregate, and random weight mutations to discover massive and complicated seek areas. The innovation of this studies lies inside the use of evolutionary neural networks to enhance the accuracy, convergence speed, and generalization capabilities of deep mastering algorithms while managing big virtual datasets. Empirical findings imply that the proposed technique notably improves the effectiveness of deep mastering algorithms in coping with sizeable digital datasets.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100126"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143403101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent advancements and progress in development of ferroelectric field effect transistor: A review","authors":"Mandeep Singh,&nbsp;Nakkina Sai Teja,&nbsp;Tarun Chaudhary,&nbsp;Balwinder Raj","doi":"10.1016/j.memori.2025.100130","DOIUrl":"10.1016/j.memori.2025.100130","url":null,"abstract":"<div><div>The robust application of ferroelectric materials in various disciplines has resulted in the development of significantly more accurate and potent FeFETs, which have the potential to deliver more promising non-volatile memory and synaptic devices than traditional ones. The present study illustrates the fundamental concepts, operation, and construction of FeFETs and presents a methodology to determine suitable ferroelectric materials, the make-up of gate stacks, and the advantages that are necessary for an efficient and commercial FeFET. Among various ferroelectric-based FETs, the HfO₂-based FeEFT has exhibited much more potential and huge advantages such as thin profiles, high polarisation, data retention, and endurance, which have been thoroughly explored in the present study. This paper discusses the contemporary challenges in device design by focusing primarily on the performance parameters such as CMOS compatibility of ferroelectric materials, gate leakage current, depolarisation fields, and a few other factors. Considering these factors will ultimately influence the critical concerns associated with devising design and practical limitations.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"10 ","pages":"Article 100130"},"PeriodicalIF":0.0,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Simulation of Balanced Ternary Priority Encoder","authors":"Aadarsh Ganesh Goenka ,&nbsp;Shyamali Mitra ,&nbsp;Harsh Maheshwari ,&nbsp;Nibaran Das","doi":"10.1016/j.memori.2024.100118","DOIUrl":"10.1016/j.memori.2024.100118","url":null,"abstract":"<div><p>The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions involving large range of numbers, whereas, the literature is confined to very basic functions. The proposed balanced priority encoder circuit that uses three logic symbols <em>i.e.</em> <span><math><mrow><mo>−</mo><mn>1</mn><mo>,</mo><mn>0</mn></mrow></math></span> and <span><math><mn>1</mn></math></span>. In this study, we develop the design and architecture of a Ternary Priority Encoder circuit with an estimation of its time complexity. The intricacy of the circuit under consideration is supposed to highlight the capabilities of the ternary logic system. The flexibility of the circuit lies in its implementation using simple binary counterparts. As there is no simulator available for Ternary Logic, we have developed a Balanced Ternary Logic Simulator which is freely available from <span><span>https://github.com/Aggtur11/Ternary-Logic-Simulator</span><svg><path></path></svg></span>. The logic behaviour of the proposed priority encoder circuits is verified using the developed simulator.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100118"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000215/pdfft?md5=0125d5dde1a559ad3c35ae9b6fcbac2c&pid=1-s2.0-S2773064624000215-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141846606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}