Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications","authors":"Venkata Sudhakar Chowdam ,&nbsp;Suresh Babu Potladurty ,&nbsp;Prasad Reddy karipireddy","doi":"10.1016/j.memori.2025.100123","DOIUrl":"10.1016/j.memori.2025.100123","url":null,"abstract":"<div><div>The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100123"},"PeriodicalIF":0.0,"publicationDate":"2025-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of generic vedic ALU using reversible logic","authors":"Kanchan S. Tiwari","doi":"10.1016/j.memori.2025.100121","DOIUrl":"10.1016/j.memori.2025.100121","url":null,"abstract":"<div><div>This paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to derive efficient computational methods, and reversible logic is harnessed to achieve minimal power dissipation and reduced heat generation in the ALU. The proposed ALU architecture is optimized to perform fundamental arithmetic operations: addition, subtraction, multiplication, and division; as well as bitwise logical operations: AND, OR, and XOR. Vedic mathematics techniques contribute to the reduction of critical paths and garbage outputs, enhancing the overall performance of the ALU. The design is synthesized and implemented on a device Xc7a35tcpg236 belonging to Artix-7 family of FPGA, and power consumption is evaluated and compared with conventional ALU designs. Performance parameters, including power consumption and delay, were benchmarked against existing designs. The designed ALU operates at a clock frequency of 408.197 MHz, featuring a maximum combinational path delay of 4.65 ns with input voltage of 1 V. Notable is its power efficiency, which consumes a mere 42 mW, as opposed to the conventional ALU with a power consumption of 73 mW. The Vinculum based logic of reducing bigger number to smaller ones thereby simplifying calculations is also added in the design. Incorporating Vedic reversible logic with vinculum in FPGA design introduces a novel approach leveraging parallelism and pipelining for enhanced efficiency and performance. Furthermore, the FPGA-based implementation showcases the scalability of the design for higher bit-width ALUs, highlighting its potential for integration into complex digital systems. The proposed Generic low-power Vedic ALU using reversible logic opens up new opportunities for energy-efficient computing applications, such as portable devices, embedded systems, and Internet of Things (IoT) devices. The fusion of Vedic mathematics with reversible logic offers a novel approach to design efficient ALUs, contributing to the advancement of low-power and high-performance digital circuitry.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100121"},"PeriodicalIF":0.0,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Compensation of active filter using p-q theory in photovoltaic systems","authors":"Farzane Soleimani Rudi,&nbsp;Mohammad Naser Hashemnia","doi":"10.1016/j.memori.2025.100122","DOIUrl":"10.1016/j.memori.2025.100122","url":null,"abstract":"<div><div>This work proposes an active shunt filter design for grid-connected solar systems, utilizing the p-q instantaneous power theory technique to minimize grid harmonics and reduce reactive power. As a result, the total harmonic distortion (THD) is decreased, and the power quality of the network is improved. To optimize the efficiency of solar panels and generate the switching control signal of the boost converter, the Perturb and Observe (P&amp;O) method and Pulse Width Modulation (PWM) technique are employed, respectively. The active shunt filter extracts the harmonic components of the load current using the p-q theory, which serves as a reference signal for compensation. A hysteresis method is used to control the filter current and produce the pulses for the filter switches. The designed filter reduces the harmonic distortion in the load current to approximately 29.91%. A comparison between the harmonic reference signal and the injected filter current to the three-phase grid confirms the correctness of the design. Moreover, the sinusoidal waveform of the three-phase grid currents demonstrates the effectiveness of the proposed controller. Simulation results in MATLAB validate the proposed filter, with the network current THD reduced to less than 5%, confirming the efficacy of the design.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100122"},"PeriodicalIF":0.0,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High performance memristor device from solution processed MnO2 nanowires: Tuning of resistive switching from analog to digital and underlying mechanism","authors":"Rajkumar Mandal,&nbsp;Arka Mandal,&nbsp;Nayan Pandit,&nbsp;Rajib Nath,&nbsp;Biswanath Mukherjee","doi":"10.1016/j.memori.2024.100120","DOIUrl":"10.1016/j.memori.2024.100120","url":null,"abstract":"<div><div>This study reports the synthesis of manganese dioxide (MnO₂) nanowires via the hydrothermal method and the fabrication of high-performance memristor devices using solution-processed MnO₂ nanowires. Microstructural characterizations, <em>viz</em>, XRD, SEM, EDAX and XPS of synthesized sample revealed highly crystalline structures of MnO₂ nanowires. As synthesized MnO₂ nanowires, mixed in different weight percentages with poly(methyl methacrylate) (PMMA) solution were deposited on Al electrode to form thin film memristor devices. Resistive switching with both analog and digital behaviors have been realized in Al/MnO₂-PMMA/Al device by controlling the weight percentage (wt %) of MnO₂ in the composite. When the MnO₂ wt % in the composite was low (PMMA: MnO₂ = 1:1), the device exhibited analog type switching, while, the higher concentration of MnO₂ produced digital types of switching. The On/Off current ratio of the device increased gradually with increase in MnO₂ wt %, reaching the highest switching ratio, <em>ca.</em> 10⁶ and excellent endurance (&gt;10⁴ s) for PMMA:MnO₂ = 1:8. Temperature dependent charge transport behavior and impedance spectroscopy was further carried out to explain the underlying resistive switching mechanism of the device.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100120"},"PeriodicalIF":0.0,"publicationDate":"2024-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Simulation of Balanced Ternary Priority Encoder","authors":"Aadarsh Ganesh Goenka ,&nbsp;Shyamali Mitra ,&nbsp;Harsh Maheshwari ,&nbsp;Nibaran Das","doi":"10.1016/j.memori.2024.100118","DOIUrl":"10.1016/j.memori.2024.100118","url":null,"abstract":"<div><p>The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions involving large range of numbers, whereas, the literature is confined to very basic functions. The proposed balanced priority encoder circuit that uses three logic symbols <em>i.e.</em> <span><math><mrow><mo>−</mo><mn>1</mn><mo>,</mo><mn>0</mn></mrow></math></span> and <span><math><mn>1</mn></math></span>. In this study, we develop the design and architecture of a Ternary Priority Encoder circuit with an estimation of its time complexity. The intricacy of the circuit under consideration is supposed to highlight the capabilities of the ternary logic system. The flexibility of the circuit lies in its implementation using simple binary counterparts. As there is no simulator available for Ternary Logic, we have developed a Balanced Ternary Logic Simulator which is freely available from <span><span>https://github.com/Aggtur11/Ternary-Logic-Simulator</span><svg><path></path></svg></span>. The logic behaviour of the proposed priority encoder circuits is verified using the developed simulator.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100118"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000215/pdfft?md5=0125d5dde1a559ad3c35ae9b6fcbac2c&pid=1-s2.0-S2773064624000215-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141846606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric","authors":"Priyanka Agrwal,&nbsp;Ajay Kumar","doi":"10.1016/j.memori.2024.100117","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100117","url":null,"abstract":"<div><p>In this work, a high-k In_0.53Ga_0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (<em>I</em>_ON), drain current (<em>I</em>_DS), transconductance (<em>g</em>_m), energy bands, lower subthreshold swing (<em>SS</em>), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100117"},"PeriodicalIF":0.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000203/pdfft?md5=fdcd93497434b6a749024d931f053daa&pid=1-s2.0-S2773064624000203-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141541238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"First passage times of charge transport and entropy change","authors":"V.V. Ryazanov","doi":"10.1016/j.memori.2024.100116","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100116","url":null,"abstract":"<div><p>All real physical processes, including of the first-passage time, occur with a change in entropy. This circumstance is not taken into account when studying the first-passage time, but is illustrated in this article using the example of electron transfer through a metallic double dot. The statistics of the first-passage time of a random process <em>N(t)</em> for electrons transferred through a metallic double dot is considered. The expressions for the average first-passage time are compared with and without taking into account the change in entropy during this time. External influences on the average value of the first-passage time are considered for the case of <em>DC</em> bias voltage.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100116"},"PeriodicalIF":0.0,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000197/pdfft?md5=8d6365dde63a79fcdeca2275bddb3e2c&pid=1-s2.0-S2773064624000197-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141486477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RRAM based processing-in-memory for efficient intelligent vision tasks at the edge","authors":"Ashwani Kumar ,&nbsp;Sai Sukruth Bezugam","doi":"10.1016/j.memori.2024.100115","DOIUrl":"10.1016/j.memori.2024.100115","url":null,"abstract":"<div><p>The work presents a proof-of-concept methodology for at edge visual data storage and processing-in-memory (PIM) as visual data preprocessing inspired from the biological visual system pipeline. This work proposes a methodology to improve the contrast of low-light low-contrast image by carefully modulating the conductance of memristive kind oxide-based resistive memory (RRAM)device. We present the level of contrast enhancement using conductance modulation of different non-filamentary RRAMs with different material stacks and also analyze the impact of RRAM variability on the contrast enhancement. For intelligent vision tasks, we implement artificial neural network (ANN) to perform the image classification and shows the best-case improvement of <span><math><mo>∼</mo></math></span> 1500 epochs (<span><math><mo>∼</mo></math></span> 74%) using RRAM based PIM. We also implement a large sized ANN “Efficient-Det Network” to perform object recognition on low-light low-contrast dataset ”Ex-Dark” to evaluate the proposed method using PIM layer. The result shows 8% higher mAP than network without a PIM layer. The present work is a step towards the development of efficient hybrid visual system for intelligent vision tasks at edge.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100115"},"PeriodicalIF":0.0,"publicationDate":"2024-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000185/pdfft?md5=add14767a7cfd0e098a0b9be5114842a&pid=1-s2.0-S2773064624000185-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141137248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Erratum regarding missing Declaration of Competing Interest statements in previously published articles","authors":"","doi":"10.1016/j.memori.2024.100113","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100113","url":null,"abstract":"","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100113"},"PeriodicalIF":0.0,"publicationDate":"2024-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000161/pdfft?md5=5ca578f512b1f71c117c362c0404f3cd&pid=1-s2.0-S2773064624000161-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140951614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Realization of multi-functional features with ZnO nanosheets/p-Si based electronic device for energy harvesting and memristive switching","authors":"Parasuraman R ,&nbsp;Rathnakannan K","doi":"10.1016/j.memori.2024.100114","DOIUrl":"10.1016/j.memori.2024.100114","url":null,"abstract":"<div><p>This work investigates and reports on the fabrication of a ZnO nanosheets/p-Si heterojunction energy harvester. The proposed nanostructure device exhibits two key functionalities: energy harvesting and memristive characteristics. This allows the device to perform multiple tasks. The ZnO nanostructure sheet was grown using a hydrothermal method. To minimize defect states at the electrode-substrate interface, an optimal phosphorus doping process was employed to achieve minimal substrate sheet resistance. Under an applied pushing force of 0.259 kgf, the energy harvester generated an output voltage and current of 0.5548 V and 44 μA, respectively. The proposed structure produces an output of 24.41 μW at 13 Hz for 2000 cycles. Investigation of the device's transfer characteristics revealed memristive behavior with an on/off ratio of 10⁷. These findings suggest that the multifunctional ZnO nanosheets/p-Si electronic device reported here has promising potential for applications in the Internet of Things (IoT).</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100114"},"PeriodicalIF":0.0,"publicationDate":"2024-05-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000173/pdfft?md5=e2703107978af818c579817cbc316862&pid=1-s2.0-S2773064624000173-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141023779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}