Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Frequency selective asymmetric coupled-fed (ACS) antenna using additive manufacturing","authors":"Sanjee Lamsal ,&nbsp;Afahaene Uya ,&nbsp;Srikanth Itapu ,&nbsp;Frank X. Li ,&nbsp;Pedro Cortes ,&nbsp;Vamsi Borra","doi":"10.1016/j.memori.2024.100111","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100111","url":null,"abstract":"<div><p>In this study, the development of diverse antenna designs using additive manufacturing processes, specifically spanning from L-band to K-band is proposed. All designs are implemented on a flexible FR4 substrate to make them suitable for wearable sensors and biomedical applications. The fabrication process involves the utilization of aerosol jet printing with nanoparticle silver ink, followed by curing in a vacuum chamber. Additionally, screen printing with copper paste is employed as another method, with subsequent curing in a laminator. The reflection coefficient (S11) and radiation patterns for the simulated design and fabricated samples were found to align closely. The achieved return loss consistently reaching −10 dB across fairly large operating frequency range underscores the efficacy of the proposed antennas and their associated additive manufacturing mechanisms. The design and simulation were performed using Ansys high frequency structural simulator (HFSS), and the parameters under test for the fabricated antennas were validated using a vector network analyzer (VNA) to assess overall performance.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100111"},"PeriodicalIF":0.0,"publicationDate":"2024-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000136/pdfft?md5=a045b7b1b005e5d65c337d5adb5ffc64&pid=1-s2.0-S2773064624000136-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140951613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving signal isolation in hybrid RF duplexer utilizing a band-pass filter","authors":"Amir Ali Mohammad Khani ,&nbsp;Ali Soldoozy ,&nbsp;Farzane Soleimani Rudi ,&nbsp;Elham Zandi","doi":"10.1016/j.memori.2024.100112","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100112","url":null,"abstract":"<div><p>This study deals with a passive RF duplexer integrated with a two-notch band. To design the model, a band-pass filter is considered. Using micro-strip technology, the RF duplexer substation is simulated. It is a rectangular in parallel coupling with frequency bands of 1 and 5 GHz while existing three ports. Moreover, to enhance the impedance coefficient and decrease the admittance, the method of complementary paired resonators is taken into account. Furthermore, scattering parameters were used by the step impedance method to make an integrated monolayer substrate from signal branching in duplex mode. Thus, the band-pass filter making the frequency cut-off bands allows designing GSM-4G radars. The low cut-off microwave band is included in these bands at the 77 MHz central frequency and the second cut-off band for GSM-4G radars at the 437 MHz central frequency. The duplexer has the total dimensions of 14 mm × 99 mm and the presented RF duplexer is simulated in CST.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100112"},"PeriodicalIF":0.0,"publicationDate":"2024-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000148/pdfft?md5=eabc26f9b5b78d298dce26adddac8b9d&pid=1-s2.0-S2773064624000148-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140948341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Towards wake-up free ferroelectrics and scaling: Al-doped HZO and its crystallographic texture","authors":"Ayse Sünbül ,&nbsp;David Lehninger ,&nbsp;Amir Pourjafar ,&nbsp;Shouzhuo Yang ,&nbsp;Franz Müller ,&nbsp;Ricardo Olivo ,&nbsp;Thomas Kämpfe ,&nbsp;Konrad Seidel ,&nbsp;Lukas Eng ,&nbsp;Maximilian Lederer","doi":"10.1016/j.memori.2024.100110","DOIUrl":"10.1016/j.memori.2024.100110","url":null,"abstract":"<div><p>Ferroelectric (FE) hafnium zirconium oxide (HZO) is an excellent candidate for data storage applications. However, it has some reliability limitations such as imprint and retention. Herein, we explore Al doping of HZO to overcome these limitations. FE behavior is tuned by the aluminum (Al) concentrations in the films and by annealing temperature. A correlation is done between electrical behavior, crystallographic texture, and FE phases determined by grazing-incidence X-ray diffraction (GIXRD) measurements. Reduced coercive field (2E<span><math><msub><mrow></mrow><mrow><mi>c</mi></mrow></msub></math></span>) values and wake-up free HZO-based ferroelectrics are explored. We show the tunability of remanent polarization (2P<span><math><msub><mrow></mrow><mrow><mi>r</mi></mrow></msub></math></span>) and 2E<span><math><msub><mrow></mrow><mrow><mi>c</mi></mrow></msub></math></span> with respect to Al-doping concentration and anneal temperature, hence crystallographic texture.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100110"},"PeriodicalIF":0.0,"publicationDate":"2024-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000124/pdfft?md5=445e0ff8e7f5c9c884fff43f49e16f99&pid=1-s2.0-S2773064624000124-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141028383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications","authors":"Abhishek Sahu,&nbsp;Abhishek Kumar,&nbsp;Anurag Dwivedi,&nbsp;Shree Prakash Tiwari","doi":"10.1016/j.memori.2024.100108","DOIUrl":"10.1016/j.memori.2024.100108","url":null,"abstract":"<div><p>Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain <span><math><mi>β</mi></math></span> values <span><math><mrow><mo>&gt;</mo><mn>1100</mn></mrow></math></span>, <span><math><mrow><msub><mrow><mi>f</mi></mrow><mrow><mi>t</mi></mrow></msub><mo>&gt;</mo><mn>500</mn></mrow></math></span> GHz, <span><math><mrow><msub><mrow><mi>f</mi></mrow><mrow><mi>m</mi><mi>a</mi><mi>x</mi></mrow></msub><mo>&gt;</mo><mn>1300</mn></mrow></math></span> GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of <span><math><mrow><mo>∼</mo><mn>1</mn><mo>.</mo><mn>3</mn></mrow></math></span> ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the <span><math><mi>β</mi></math></span> value for WED-based devices when subjected to temperatures exceeding <span><math><mrow><mn>340</mn></mrow></math></span> K. In contrast, BED-based devices demonstrate a comparatively smaller variation in <span><math><mi>β</mi></math></span> at temperatures above <span><math><mrow><mn>340</mn></mrow></math></span> K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100108"},"PeriodicalIF":0.0,"publicationDate":"2024-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000100/pdfft?md5=c694a161afbe2608c45c4d4abd28f820&pid=1-s2.0-S2773064624000100-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140763480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Simulation of Reversible Logic Gate Using HCS Macro-Model","authors":"Snigdha Chowdhury Kolay ,&nbsp;Amrita Chatterjee ,&nbsp;Subrata Chattopadhyay","doi":"10.1016/j.memori.2024.100109","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100109","url":null,"abstract":"<div><p>—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100109"},"PeriodicalIF":0.0,"publicationDate":"2024-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000112/pdfft?md5=749770b78b3f743288f1fc9b4fe3ca83&pid=1-s2.0-S2773064624000112-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140639348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully active and highly reliable combined ring voltage controlled CMOS oscillator","authors":"Ilghar Rezaei ,&nbsp;Ava Salmanpour ,&nbsp;Ali Soldoozy ,&nbsp;Toktam Aghaee","doi":"10.1016/j.memori.2024.100107","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100107","url":null,"abstract":"<div><p>Leveraging two types of enhanced delay stages to form an oscillation loop, results in a highly reliable CMOS ring oscillator versus external interventions. The idea is investigated via symbolic delay calculations and the HSPICE circuit simulator while 0.18 μm CMOS is exploited. Based on two described inverters, three-ring oscillators are presented. The two ones use only one type of delay stage while the third is combined using two basic inverters and a single current-starved inverter. The basic type inverter is the fastest while is sensitive to power supply and temperature variations. On the other hand, the sensitivity of the current starved inverter is acceptable but this delay stage shows a large delay time, reducing oscillation frequency. This work tries to address this tradeoff between speed and sensitivity by proposing an oscillation loop. The delay times analysis and simulation results verify the robust performance of the proposed oscillator.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100107"},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000094/pdfft?md5=c13283fe13871a3ff3194ba7184b2491&pid=1-s2.0-S2773064624000094-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140645537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating convolutional neural networks for improved software engineering: A Collaborative and unbalanced data Perspective","authors":"Mohammadreza Nehzati","doi":"10.1016/j.memori.2024.100106","DOIUrl":"10.1016/j.memori.2024.100106","url":null,"abstract":"<div><p>This study pioneers the tailored application of Convolutional Neural Networks (CNNs) for addressing the challenge of unbalanced data in software engineering, a relatively unexplored domain for CNN utilization. Unlike conventional methods, our framework demonstrates a significant precision uplift of up to 15% in software classification tasks, specifically enhancing minority class sample accuracy. This research not only delineates a novel CNN-based approach that outperforms traditional data balancing techniques but also underscores the strategic integration of AI to bolster software engineering processes. By pinpointing the ethical implications, our findings advocate for a conscientious adoption of AI, ensuring software development advances equitably and efficiently.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100106"},"PeriodicalIF":0.0,"publicationDate":"2024-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000082/pdfft?md5=42835d178c5411492a9767c94338cbaa&pid=1-s2.0-S2773064624000082-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140757846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programmable delay line with inherent duty cycle correction","authors":"Siva Charan Nimmagadda,&nbsp;Hari Bilash Dubey","doi":"10.1016/j.memori.2024.100105","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100105","url":null,"abstract":"<div><p>In the recent HBM2E IO design, clock is transmitted differentially to the external DRAM and duty cycle distortion (DCD) could add to the differential clock due to traversing multiple stages in DRAM. At higher data rates, the DCD from the differential clock imposes restrictions on the timing margins. In the current work, Tx clock path is added with DCC feature to compensate for any DCD errors introduced by the clock network in the external DRAM. Linearity of the DCC is critical metric when the clock is differential and running at high speed. A new programmable delay line with inherent DCC design with good linearity is presented in this paper.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100105"},"PeriodicalIF":0.0,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000070/pdfft?md5=f2f2eb80f462eba8da92003848437ec8&pid=1-s2.0-S2773064624000070-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140542761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An ultra-thin meta-material including graphene patterns: Coupling application","authors":"Amir Ali Mohammad Khani ,&nbsp;Ava Salmanpour ,&nbsp;Ali Soldoozy ,&nbsp;Elham Zandi","doi":"10.1016/j.memori.2024.100103","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100103","url":null,"abstract":"<div><p>Here a novel ultra-thin meta-material structure is proposed, including periodic arrays of graphene rings, disks, and ribbons and SiO₂ dielectric as spacer between graphene patterns layers at the terahertz (THz) range. The introduced device can couple electromagnetic waves by considering reflection and transmission channels as outputs. Electromagnetic wave coupling depends on the parameters design and the device thickness. The proposed structure can couple electromagnetic waves in multi-band and close frequencies including 2 THz, 4 THz, 6 THz, 7.5 THz, and 9.5 THz. By considering the impedance matching concept, an equivalent circuit model (ECM) is developed for the proposed meta-material. Also, the device stability is investigated in various physical coefficients, geometrical parameters, and incident wave angles to ensure optical applications such as sensors, indoor communications, security, and medical imaging.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100103"},"PeriodicalIF":0.0,"publicationDate":"2024-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000057/pdfft?md5=eeb347f17cf3ff5285ee15a6723d5e1c&pid=1-s2.0-S2773064624000057-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139941894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and analysis of novel La:HfO2 gate stacked ferroelectric tunnel FET for non-volatile memory applications","authors":"Neha Paras ,&nbsp;Shiromani Balmukund Rahi ,&nbsp;Abhishek Kumar Upadhyay ,&nbsp;Manisha Bharti ,&nbsp;Young Suh Song","doi":"10.1016/j.memori.2024.100101","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100101","url":null,"abstract":"<div><p>Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO₂) possessing ferroelectric properties. This material is of special interest since it is based on lead-free, simple binary oxide of HfO₂, and has excellent endurance property (1 × 10⁹ field cycles without fatigue. There exists substantial information about the material aspects of La:HfO₂ but it lacks proven application potential for CMOS-compatible low-power memory design. In this work, 10 % La metal cation fraction of HfO₂ (La:HfO₂) is proposed as the gate stack material in tunnel FET (TFET) for its potential as a memory device. 2D device simulations are carried out to show that the proposed ferroelectric TFET (FeTFET) provides the largest memory window (MW) as compared to present perovskite ferroelectric materials such as PZT, SBT (SrBi₂Ta₂O₉) and silicon doped (4.6 % Si in HfO₂) hafnium oxide (Si:HfO₂). The larger window is attributed to greater polarization, and the calculation of MW is quantified by the shift in threshold voltage (V_th). The simulations carried out in this work suggest that La:HfO₂ can be adopted as a potential ferroelectric material to target low-power FeTFET design at significantly reduced ferroelectric layer thickness.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100101"},"PeriodicalIF":0.0,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000033/pdfft?md5=22395a41426eb2f704ddea26a21f4352&pid=1-s2.0-S2773064624000033-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139714077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}