Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"RRAM based processing-in-memory for efficient intelligent vision tasks at the edge","authors":"Ashwani Kumar ,&nbsp;Sai Sukruth Bezugam","doi":"10.1016/j.memori.2024.100115","DOIUrl":"10.1016/j.memori.2024.100115","url":null,"abstract":"<div><p>The work presents a proof-of-concept methodology for at edge visual data storage and processing-in-memory (PIM) as visual data preprocessing inspired from the biological visual system pipeline. This work proposes a methodology to improve the contrast of low-light low-contrast image by carefully modulating the conductance of memristive kind oxide-based resistive memory (RRAM)device. We present the level of contrast enhancement using conductance modulation of different non-filamentary RRAMs with different material stacks and also analyze the impact of RRAM variability on the contrast enhancement. For intelligent vision tasks, we implement artificial neural network (ANN) to perform the image classification and shows the best-case improvement of <span><math><mo>∼</mo></math></span> 1500 epochs (<span><math><mo>∼</mo></math></span> 74%) using RRAM based PIM. We also implement a large sized ANN “Efficient-Det Network” to perform object recognition on low-light low-contrast dataset ”Ex-Dark” to evaluate the proposed method using PIM layer. The result shows 8% higher mAP than network without a PIM layer. The present work is a step towards the development of efficient hybrid visual system for intelligent vision tasks at edge.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100115"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000185/pdfft?md5=add14767a7cfd0e098a0b9be5114842a&pid=1-s2.0-S2773064624000185-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141137248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Frequency selective asymmetric coupled-fed (ACS) antenna using additive manufacturing","authors":"Sanjee Lamsal ,&nbsp;Afahaene Uya ,&nbsp;Srikanth Itapu ,&nbsp;Frank X. Li ,&nbsp;Pedro Cortes ,&nbsp;Vamsi Borra","doi":"10.1016/j.memori.2024.100111","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100111","url":null,"abstract":"<div><p>In this study, the development of diverse antenna designs using additive manufacturing processes, specifically spanning from L-band to K-band is proposed. All designs are implemented on a flexible FR4 substrate to make them suitable for wearable sensors and biomedical applications. The fabrication process involves the utilization of aerosol jet printing with nanoparticle silver ink, followed by curing in a vacuum chamber. Additionally, screen printing with copper paste is employed as another method, with subsequent curing in a laminator. The reflection coefficient (S11) and radiation patterns for the simulated design and fabricated samples were found to align closely. The achieved return loss consistently reaching −10 dB across fairly large operating frequency range underscores the efficacy of the proposed antennas and their associated additive manufacturing mechanisms. The design and simulation were performed using Ansys high frequency structural simulator (HFSS), and the parameters under test for the fabricated antennas were validated using a vector network analyzer (VNA) to assess overall performance.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100111"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000136/pdfft?md5=a045b7b1b005e5d65c337d5adb5ffc64&pid=1-s2.0-S2773064624000136-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140951613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Erratum regarding missing Declaration of Competing Interest statements in previously published articles","authors":"","doi":"10.1016/j.memori.2024.100113","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100113","url":null,"abstract":"","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100113"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000161/pdfft?md5=5ca578f512b1f71c117c362c0404f3cd&pid=1-s2.0-S2773064624000161-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140951614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully active and highly reliable combined ring voltage controlled CMOS oscillator","authors":"Ilghar Rezaei ,&nbsp;Ava Salmanpour ,&nbsp;Ali Soldoozy ,&nbsp;Toktam Aghaee","doi":"10.1016/j.memori.2024.100107","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100107","url":null,"abstract":"<div><p>Leveraging two types of enhanced delay stages to form an oscillation loop, results in a highly reliable CMOS ring oscillator versus external interventions. The idea is investigated via symbolic delay calculations and the HSPICE circuit simulator while 0.18 μm CMOS is exploited. Based on two described inverters, three-ring oscillators are presented. The two ones use only one type of delay stage while the third is combined using two basic inverters and a single current-starved inverter. The basic type inverter is the fastest while is sensitive to power supply and temperature variations. On the other hand, the sensitivity of the current starved inverter is acceptable but this delay stage shows a large delay time, reducing oscillation frequency. This work tries to address this tradeoff between speed and sensitivity by proposing an oscillation loop. The delay times analysis and simulation results verify the robust performance of the proposed oscillator.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100107"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000094/pdfft?md5=c13283fe13871a3ff3194ba7184b2491&pid=1-s2.0-S2773064624000094-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140645537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications","authors":"Abhishek Sahu,&nbsp;Abhishek Kumar,&nbsp;Anurag Dwivedi,&nbsp;Shree Prakash Tiwari","doi":"10.1016/j.memori.2024.100108","DOIUrl":"10.1016/j.memori.2024.100108","url":null,"abstract":"<div><p>Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain <span><math><mi>β</mi></math></span> values <span><math><mrow><mo>&gt;</mo><mn>1100</mn></mrow></math></span>, <span><math><mrow><msub><mrow><mi>f</mi></mrow><mrow><mi>t</mi></mrow></msub><mo>&gt;</mo><mn>500</mn></mrow></math></span> GHz, <span><math><mrow><msub><mrow><mi>f</mi></mrow><mrow><mi>m</mi><mi>a</mi><mi>x</mi></mrow></msub><mo>&gt;</mo><mn>1300</mn></mrow></math></span> GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of <span><math><mrow><mo>∼</mo><mn>1</mn><mo>.</mo><mn>3</mn></mrow></math></span> ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the <span><math><mi>β</mi></math></span> value for WED-based devices when subjected to temperatures exceeding <span><math><mrow><mn>340</mn></mrow></math></span> K. In contrast, BED-based devices demonstrate a comparatively smaller variation in <span><math><mi>β</mi></math></span> at temperatures above <span><math><mrow><mn>340</mn></mrow></math></span> K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100108"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000100/pdfft?md5=c694a161afbe2608c45c4d4abd28f820&pid=1-s2.0-S2773064624000100-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140763480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating convolutional neural networks for improved software engineering: A Collaborative and unbalanced data Perspective","authors":"Mohammadreza Nehzati","doi":"10.1016/j.memori.2024.100106","DOIUrl":"10.1016/j.memori.2024.100106","url":null,"abstract":"<div><p>This study pioneers the tailored application of Convolutional Neural Networks (CNNs) for addressing the challenge of unbalanced data in software engineering, a relatively unexplored domain for CNN utilization. Unlike conventional methods, our framework demonstrates a significant precision uplift of up to 15% in software classification tasks, specifically enhancing minority class sample accuracy. This research not only delineates a novel CNN-based approach that outperforms traditional data balancing techniques but also underscores the strategic integration of AI to bolster software engineering processes. By pinpointing the ethical implications, our findings advocate for a conscientious adoption of AI, ensuring software development advances equitably and efficiently.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100106"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000082/pdfft?md5=42835d178c5411492a9767c94338cbaa&pid=1-s2.0-S2773064624000082-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140757846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Simulation of Reversible Logic Gate Using HCS Macro-Model","authors":"Snigdha Chowdhury Kolay ,&nbsp;Amrita Chatterjee ,&nbsp;Subrata Chattopadhyay","doi":"10.1016/j.memori.2024.100109","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100109","url":null,"abstract":"<div><p>—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100109"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000112/pdfft?md5=749770b78b3f743288f1fc9b4fe3ca83&pid=1-s2.0-S2773064624000112-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140639348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"First passage times of charge transport and entropy change","authors":"V.V. Ryazanov","doi":"10.1016/j.memori.2024.100116","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100116","url":null,"abstract":"<div><p>All real physical processes, including of the first-passage time, occur with a change in entropy. This circumstance is not taken into account when studying the first-passage time, but is illustrated in this article using the example of electron transfer through a metallic double dot. The statistics of the first-passage time of a random process <em>N(t)</em> for electrons transferred through a metallic double dot is considered. The expressions for the average first-passage time are compared with and without taking into account the change in entropy during this time. External influences on the average value of the first-passage time are considered for the case of <em>DC</em> bias voltage.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100116"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000197/pdfft?md5=8d6365dde63a79fcdeca2275bddb3e2c&pid=1-s2.0-S2773064624000197-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141486477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric","authors":"Priyanka Agrwal,&nbsp;Ajay Kumar","doi":"10.1016/j.memori.2024.100117","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100117","url":null,"abstract":"<div><p>In this work, a high-k In_0.53Ga_0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (<em>I</em>_ON), drain current (<em>I</em>_DS), transconductance (<em>g</em>_m), energy bands, lower subthreshold swing (<em>SS</em>), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100117"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000203/pdfft?md5=fdcd93497434b6a749024d931f053daa&pid=1-s2.0-S2773064624000203-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141541238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programmable delay line with inherent duty cycle correction","authors":"Siva Charan Nimmagadda,&nbsp;Hari Bilash Dubey","doi":"10.1016/j.memori.2024.100105","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100105","url":null,"abstract":"<div><p>In the recent HBM2E IO design, clock is transmitted differentially to the external DRAM and duty cycle distortion (DCD) could add to the differential clock due to traversing multiple stages in DRAM. At higher data rates, the DCD from the differential clock imposes restrictions on the timing margins. In the current work, Tx clock path is added with DCC feature to compensate for any DCD errors introduced by the clock network in the external DRAM. Linearity of the DCC is critical metric when the clock is differential and running at high speed. A new programmable delay line with inherent DCC design with good linearity is presented in this paper.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100105"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000070/pdfft?md5=f2f2eb80f462eba8da92003848437ec8&pid=1-s2.0-S2773064624000070-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140542761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}