Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Towards wake-up free ferroelectrics and scaling: Al-doped HZO and its crystallographic texture","authors":"Ayse Sünbül ,&nbsp;David Lehninger ,&nbsp;Amir Pourjafar ,&nbsp;Shouzhuo Yang ,&nbsp;Franz Müller ,&nbsp;Ricardo Olivo ,&nbsp;Thomas Kämpfe ,&nbsp;Konrad Seidel ,&nbsp;Lukas Eng ,&nbsp;Maximilian Lederer","doi":"10.1016/j.memori.2024.100110","DOIUrl":"10.1016/j.memori.2024.100110","url":null,"abstract":"<div><p>Ferroelectric (FE) hafnium zirconium oxide (HZO) is an excellent candidate for data storage applications. However, it has some reliability limitations such as imprint and retention. Herein, we explore Al doping of HZO to overcome these limitations. FE behavior is tuned by the aluminum (Al) concentrations in the films and by annealing temperature. A correlation is done between electrical behavior, crystallographic texture, and FE phases determined by grazing-incidence X-ray diffraction (GIXRD) measurements. Reduced coercive field (2E<span><math><msub><mrow></mrow><mrow><mi>c</mi></mrow></msub></math></span>) values and wake-up free HZO-based ferroelectrics are explored. We show the tunability of remanent polarization (2P<span><math><msub><mrow></mrow><mrow><mi>r</mi></mrow></msub></math></span>) and 2E<span><math><msub><mrow></mrow><mrow><mi>c</mi></mrow></msub></math></span> with respect to Al-doping concentration and anneal temperature, hence crystallographic texture.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100110"},"PeriodicalIF":0.0,"publicationDate":"2024-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000124/pdfft?md5=445e0ff8e7f5c9c884fff43f49e16f99&pid=1-s2.0-S2773064624000124-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141028383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and reliability assessment of an ultra-thin body electrostatically doped bipolar transistor for mixed signal applications","authors":"Abhishek Sahu,&nbsp;Abhishek Kumar,&nbsp;Anurag Dwivedi,&nbsp;Shree Prakash Tiwari","doi":"10.1016/j.memori.2024.100108","DOIUrl":"10.1016/j.memori.2024.100108","url":null,"abstract":"<div><p>Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain <span><math><mi>β</mi></math></span> values <span><math><mrow><mo>&gt;</mo><mn>1100</mn></mrow></math></span>, <span><math><mrow><msub><mrow><mi>f</mi></mrow><mrow><mi>t</mi></mrow></msub><mo>&gt;</mo><mn>500</mn></mrow></math></span> GHz, <span><math><mrow><msub><mrow><mi>f</mi></mrow><mrow><mi>m</mi><mi>a</mi><mi>x</mi></mrow></msub><mo>&gt;</mo><mn>1300</mn></mrow></math></span> GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of <span><math><mrow><mo>∼</mo><mn>1</mn><mo>.</mo><mn>3</mn></mrow></math></span> ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the <span><math><mi>β</mi></math></span> value for WED-based devices when subjected to temperatures exceeding <span><math><mrow><mn>340</mn></mrow></math></span> K. In contrast, BED-based devices demonstrate a comparatively smaller variation in <span><math><mi>β</mi></math></span> at temperatures above <span><math><mrow><mn>340</mn></mrow></math></span> K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100108"},"PeriodicalIF":0.0,"publicationDate":"2024-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000100/pdfft?md5=c694a161afbe2608c45c4d4abd28f820&pid=1-s2.0-S2773064624000100-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140763480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and Simulation of Reversible Logic Gate Using HCS Macro-Model","authors":"Snigdha Chowdhury Kolay ,&nbsp;Amrita Chatterjee ,&nbsp;Subrata Chattopadhyay","doi":"10.1016/j.memori.2024.100109","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100109","url":null,"abstract":"<div><p>—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100109"},"PeriodicalIF":0.0,"publicationDate":"2024-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000112/pdfft?md5=749770b78b3f743288f1fc9b4fe3ca83&pid=1-s2.0-S2773064624000112-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140639348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully active and highly reliable combined ring voltage controlled CMOS oscillator","authors":"Ilghar Rezaei ,&nbsp;Ava Salmanpour ,&nbsp;Ali Soldoozy ,&nbsp;Toktam Aghaee","doi":"10.1016/j.memori.2024.100107","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100107","url":null,"abstract":"<div><p>Leveraging two types of enhanced delay stages to form an oscillation loop, results in a highly reliable CMOS ring oscillator versus external interventions. The idea is investigated via symbolic delay calculations and the HSPICE circuit simulator while 0.18 μm CMOS is exploited. Based on two described inverters, three-ring oscillators are presented. The two ones use only one type of delay stage while the third is combined using two basic inverters and a single current-starved inverter. The basic type inverter is the fastest while is sensitive to power supply and temperature variations. On the other hand, the sensitivity of the current starved inverter is acceptable but this delay stage shows a large delay time, reducing oscillation frequency. This work tries to address this tradeoff between speed and sensitivity by proposing an oscillation loop. The delay times analysis and simulation results verify the robust performance of the proposed oscillator.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100107"},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000094/pdfft?md5=c13283fe13871a3ff3194ba7184b2491&pid=1-s2.0-S2773064624000094-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140645537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrating convolutional neural networks for improved software engineering: A Collaborative and unbalanced data Perspective","authors":"Mohammadreza Nehzati","doi":"10.1016/j.memori.2024.100106","DOIUrl":"10.1016/j.memori.2024.100106","url":null,"abstract":"<div><p>This study pioneers the tailored application of Convolutional Neural Networks (CNNs) for addressing the challenge of unbalanced data in software engineering, a relatively unexplored domain for CNN utilization. Unlike conventional methods, our framework demonstrates a significant precision uplift of up to 15% in software classification tasks, specifically enhancing minority class sample accuracy. This research not only delineates a novel CNN-based approach that outperforms traditional data balancing techniques but also underscores the strategic integration of AI to bolster software engineering processes. By pinpointing the ethical implications, our findings advocate for a conscientious adoption of AI, ensuring software development advances equitably and efficiently.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100106"},"PeriodicalIF":0.0,"publicationDate":"2024-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000082/pdfft?md5=42835d178c5411492a9767c94338cbaa&pid=1-s2.0-S2773064624000082-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140757846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Programmable delay line with inherent duty cycle correction","authors":"Siva Charan Nimmagadda,&nbsp;Hari Bilash Dubey","doi":"10.1016/j.memori.2024.100105","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100105","url":null,"abstract":"<div><p>In the recent HBM2E IO design, clock is transmitted differentially to the external DRAM and duty cycle distortion (DCD) could add to the differential clock due to traversing multiple stages in DRAM. At higher data rates, the DCD from the differential clock imposes restrictions on the timing margins. In the current work, Tx clock path is added with DCC feature to compensate for any DCD errors introduced by the clock network in the external DRAM. Linearity of the DCC is critical metric when the clock is differential and running at high speed. A new programmable delay line with inherent DCC design with good linearity is presented in this paper.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100105"},"PeriodicalIF":0.0,"publicationDate":"2024-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000070/pdfft?md5=f2f2eb80f462eba8da92003848437ec8&pid=1-s2.0-S2773064624000070-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140542761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An ultra-thin meta-material including graphene patterns: Coupling application","authors":"Amir Ali Mohammad Khani ,&nbsp;Ava Salmanpour ,&nbsp;Ali Soldoozy ,&nbsp;Elham Zandi","doi":"10.1016/j.memori.2024.100103","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100103","url":null,"abstract":"<div><p>Here a novel ultra-thin meta-material structure is proposed, including periodic arrays of graphene rings, disks, and ribbons and SiO₂ dielectric as spacer between graphene patterns layers at the terahertz (THz) range. The introduced device can couple electromagnetic waves by considering reflection and transmission channels as outputs. Electromagnetic wave coupling depends on the parameters design and the device thickness. The proposed structure can couple electromagnetic waves in multi-band and close frequencies including 2 THz, 4 THz, 6 THz, 7.5 THz, and 9.5 THz. By considering the impedance matching concept, an equivalent circuit model (ECM) is developed for the proposed meta-material. Also, the device stability is investigated in various physical coefficients, geometrical parameters, and incident wave angles to ensure optical applications such as sensors, indoor communications, security, and medical imaging.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100103"},"PeriodicalIF":0.0,"publicationDate":"2024-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000057/pdfft?md5=eeb347f17cf3ff5285ee15a6723d5e1c&pid=1-s2.0-S2773064624000057-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139941894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and analysis of novel La:HfO2 gate stacked ferroelectric tunnel FET for non-volatile memory applications","authors":"Neha Paras ,&nbsp;Shiromani Balmukund Rahi ,&nbsp;Abhishek Kumar Upadhyay ,&nbsp;Manisha Bharti ,&nbsp;Young Suh Song","doi":"10.1016/j.memori.2024.100101","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100101","url":null,"abstract":"<div><p>Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO₂) possessing ferroelectric properties. This material is of special interest since it is based on lead-free, simple binary oxide of HfO₂, and has excellent endurance property (1 × 10⁹ field cycles without fatigue. There exists substantial information about the material aspects of La:HfO₂ but it lacks proven application potential for CMOS-compatible low-power memory design. In this work, 10 % La metal cation fraction of HfO₂ (La:HfO₂) is proposed as the gate stack material in tunnel FET (TFET) for its potential as a memory device. 2D device simulations are carried out to show that the proposed ferroelectric TFET (FeTFET) provides the largest memory window (MW) as compared to present perovskite ferroelectric materials such as PZT, SBT (SrBi₂Ta₂O₉) and silicon doped (4.6 % Si in HfO₂) hafnium oxide (Si:HfO₂). The larger window is attributed to greater polarization, and the calculation of MW is quantified by the shift in threshold voltage (V_th). The simulations carried out in this work suggest that La:HfO₂ can be adopted as a potential ferroelectric material to target low-power FeTFET design at significantly reduced ferroelectric layer thickness.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100101"},"PeriodicalIF":0.0,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000033/pdfft?md5=22395a41426eb2f704ddea26a21f4352&pid=1-s2.0-S2773064624000033-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139714077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Flexible devices for eco-sustainable electronics: Natural polysaccharide as gate dielectric in organic transistors","authors":"Gargi Konwar,&nbsp;Shree Prakash Tiwari","doi":"10.1016/j.memori.2024.100102","DOIUrl":"https://doi.org/10.1016/j.memori.2024.100102","url":null,"abstract":"<div><p>In this paper, firstly, reports on use of various nature originated polysaccharides as gate dielectric candidates for organic field effect transistors (OFETs) to achieve eco-friendliness and eventual biodegradability in devices, are summarized. To emphasize the same, the performance of flexible OFETs fabricated with cyanoethyl cellulose (CEC), a synthetically modified cellulose as gate dielectric is comprehensively investigated. A widely studied TIPS-pentacene: PS blend is used to form the active layer in these devices, showing a p-channel transistor operation at a low voltage of −5 V. Along with high performance, these devices exhibited excellent repeatability and shelf life up to 10 months in ambient conditions. Effect of repeatability, bias-stress, and bending stability were investigated to confirm the decent electrical and bending stability. The device can sustain the transistor performance even after application of 200 bending cycles. Moreover, the effect of annealing temperature on transistor performance was studied to observe their suitability in real applications. These findings suggest that polysaccharides can be suitable gate dielectric for eco-sustainable electronics.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100102"},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000045/pdfft?md5=f116b84a2dcd6a1a11cec43a683c02e3&pid=1-s2.0-S2773064624000045-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139699496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Trends and challenges in design of embedded BCH error correction codes in multi-levels NAND flash memory devices","authors":"Saeideh Nabipour ,&nbsp;Javad Javidan ,&nbsp;Rolf Drechsler","doi":"10.1016/j.memori.2024.100099","DOIUrl":"10.1016/j.memori.2024.100099","url":null,"abstract":"<div><p>Recently, there has been a growing concern regarding the dependability of NAND flash cells, notably as the scale of their features reduces. To address this issue, implementing error correction codes (ECC) proves to be an effective solution. Among the various methods, BCH coding has gained significant interest because of its exceptional error correction capabilities. Over the last decades, there has been much research on BCH decoder design to meet the demand for reduced hardware complexities, minimized delay performance, and lower power dissipation to enable BCH decoders and their VLSI implementations to facilitate different code lengths and rates of code. This paper surveys the trends and challenges associated with BCH decoder in NAND flash memory devices, the possible solutions for overcoming of time and area overhead in architecture of BCH decoder block and an examination of the extent to which present architectures will respond to the escalating requirements on data transfer rate, bit error rate (BER) performance, power consumption, and silicon area that will be essential for the extensive acceptance of BCH code in applications that will emerge in the near future. To demonstrate the need for such solutions, we present rigorous experimental data on BCH error correction codes on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several area-delay efficient techniques, including three low-latency decoding strategies for implementing the BCH decoder: pipeline method, re-encoding scheme, and parallelization method, and various hardware optimization strategies for the BCH decoder, such as three area-efficient syndrome block architectures, four error locator polynomial detection algorithms, and four error position identification algorithms using the Chien search method. We investigate the increase in reliability that each of these methods brings. We also briefly address future directions that these methods and flash memory techniques could evolve into the future.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100099"},"PeriodicalIF":0.0,"publicationDate":"2024-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S277306462400001X/pdfft?md5=b040c28930a49cd5377dfcc947483cc1&pid=1-s2.0-S277306462400001X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139634445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}