Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Design of fully differential fast SCL Schmitt-trigger delay element with tunable delay and hysteresis in design and run-time","authors":"Saeideh Pahlavan ,&nbsp;M.B. Ghaznavi-Ghoushchi ,&nbsp;Mostafa Shooshtari","doi":"10.1016/j.memori.2023.100036","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100036","url":null,"abstract":"<div><p>Tuning the delay of the circuit during the circuit performance can give a chance to a circuit to reduce Process, Voltage and Temperature (PVT) effects on delay and frequency by resetting its delay in feedback. This paper presented a full differential Schmitt-trigger (ST) with tunable delay and hysteresis. The delay-hysteresis setting is done in the design phase by tuning the biasing current, sizing, bias voltage and also during the execute phase (run time) by a digital bit and restructuring the circuit and delay route. The presented ST can have high and low delays with different frequencies using a digital bit in the circuit. This can help the band selection for multi-band applications. A Flip Voltage Follower (FVF) circuit is used for the current tail to increase the current and increase the frequency bands. In this Schmitt-trigger delay changes associated with restructuring result in a 40 % power reduction. A circuit analysis for the equivalent circuit of the presented circuit has also been done and the factors affecting the frequency and delay change have been analyzed and investigated in the simulation. Monte Carlo and PVT analysis have also been performed for circuit accuracy. Power changing with an incremental delay in CMOS is improved and almost monotonous by designing Source-Coupled-Logic (SCL) Schmitt-trigger.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100036"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An efficient read approach for memristive crossbar array","authors":"Pravanjan Samanta ,&nbsp;Dev Narayan Yadav ,&nbsp;Partha Pratim Das ,&nbsp;Indranil Sengupta","doi":"10.1016/j.memori.2023.100047","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100047","url":null,"abstract":"<div><p>Resistive random access memories (ReRAM) have drawn attention of researchers due to their unique properties with applications in in-memory computing, which allows storage and computation in the same unit. This mitigates one of the major limitations in current computing architectures, where for each computation we require to move data from memory to processor or vice versa, which incurs immense amount of energy overheads. Among the various technologies for implementing ReRAM, memristor is considered to be one of the most desirable candidates due to its small size, low power consumption, and high data retention. Such ReRAM systems are often fabricated in the form of crossbar for compact layout. However, they suffer from various challenges, one of the major ones being the sneak-path problem during reading of cell values. The read operation is mostly disturbed by sneak-path currents that can result in incorrect reading of the cell. This paper presents a new approach for reading the cell values in memristive crossbars, which is capable of avoiding erroneous read operations caused by sneak-paths. It also supports parallel operations whereby multiple memristor states can be read in a single cycle. A straightforward approach for reading all the cells in an <span><math><mrow><mi>n</mi><mo>×</mo><mi>n</mi></mrow></math></span> crossbar, where the read operation is performed sequentially, requires <span><math><mrow><mi>O</mi><mrow><mo>(</mo><msup><mrow><mi>n</mi></mrow><mrow><mn>2</mn></mrow></msup><mo>)</mo></mrow></mrow></math></span> cycles, whereas the proposed approach requires <span><math><mrow><mi>O</mi><mrow><mo>(</mo><mi>n</mi><mo>)</mo></mrow></mrow></math></span> cycles.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100047"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"MPEG/H256 video encoder with 6T/8T hybrid memory architecture for high quality output at lower supply","authors":"Priyanka Sharma ,&nbsp;Vaibhav Neema ,&nbsp;Santosh Kumar Vishvakarma ,&nbsp;Shailesh Singh Chouhan","doi":"10.1016/j.memori.2023.100028","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100028","url":null,"abstract":"<div><p>The use of Multimedia video content is increased rapidly in the past decade, and most multimedia video content is used by mobile phone users. Multimedia video processing consumes significant power during video compression, and thus low power multimedia video compression is essential for battery operated devices. Moving Picture Experts Group (MPEG) Video encoding is giving a higher compression rate and low bandwidth requirement. Conventional MPEG Video encoding architecture uses the conventional 6T memory cells to store video frames for further compression processing. The failure probability of 6T cells is significantly large (0.0988 at 600 mV supply voltage), leading to a decrease in the output quality of the encoded video. From the hybrid memory matrix formulation, it is calculated that storing higher-order MSB bits in highly stable memory cells will provide high-quality video encoding processing as compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. Hence, in this research work instant of using conventional 6T memory cells during video encoding processing, a unique Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSB’s) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSB’s) are stored in the conventional 6T bit cells for high-quality video encoding processing. This research article also proposes a separate memory peripheral circuitry for hybrid memory architecture for video encoding techniques. In addition, this article proposes a unique architecture for parallel video processing with the use of a hybrid pixel memory array. The failure probability of 6T and 8T at the worst failure corner (FS corner for read and SF corner for write) is simulated for 30000 Monte-Carlo simulations points at 45 nm CMOS technology node using CADENCE EDA tool. For the simulation work here, a standard Common Intermediate Format/Quarter Common Intermediate Format (CIF/QCIF) Coastguard video sample is used and for output quality here average PSNR method is used and simulation work is performed using the MATLAB tool.</p><p>The worst PSNR for conventional 6T memory array and Hybrid memory array at 600 mV supply voltage shows improvement in worst minimum PSNR as 6.43 dB is calculated. 30% less power consumption to conventional memory architecture.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100028"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A performance-centric ML-based multi-application mapping technique for regular Network-on-Chip","authors":"Jitesh Choudhary ,&nbsp;Chitrapu Sai Sudarsan ,&nbsp;Soumya J.","doi":"10.1016/j.memori.2023.100059","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100059","url":null,"abstract":"<div><p>This research article discusses the challenges faced by the Network-on-Chip (NoC) architecture due to increased integration density and proposes a novel fault-tolerant multi-application mapping approach called ”FANC.” The approach is based on Machine Learning (ML) and can provide solutions for unseen graphs and topologies without prior training. The proposed technique uses an ML-based model to extract relevant information from the search data and incorporate it into the search process. This results in a more robust model with a higher convergence rate and solution quality. The approach is evaluated using a variety of simulation parameters, such as communication cost, network latency, throughput, and power usage. Static simulations are performed in a Python programming environment, while dynamic simulations are performed with a SystemC-based cycle-accurate NoC simulator and the Orion2.0 Power tool. The results show that FANC reduces communication costs by 266%. It also improves network latency by 9%, throughput by 1%, and power consumption by 7%. The approach also simplifies and minimizes the search area in the design exploration process and can be used as an auxiliary component for other optimization algorithms.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100059"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploiting device-level non-idealities for adversarial attacks on ReRAM-based neural networks","authors":"Tyler McLemore,&nbsp;Robert Sunbury,&nbsp;Seth Brodzik,&nbsp;Zachary Cronin,&nbsp;Elias Timmons,&nbsp;Dwaipayan Chakraborty","doi":"10.1016/j.memori.2023.100053","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100053","url":null,"abstract":"<div><p>Resistive memory (ReRAM) or memristor devices offer the prospect of more efficient computing. While memristors have been used for a variety of computing systems, their usage has gained significant popularity in the domain of deep learning. Weight matrices in deep neural networks can be mapped to crossbar architectures with memristive junctions, generally resulting in superior performance and energy efficiency. However, the nascent nature of ReRAM technology is directly associated with the presence of inherent non-idealities in the ReRAM devices currently available. Deep neural networks have already been shown to be susceptible to adversarial attacks, often by targeting vulnerabilities in the networks’ internal representation of input data. In this paper, we explore the causal relationship between device-level non-idealities in ReRAM devices and the classification performance of memristor-based neural network accelerators. Specifically, our aim is to generate images which bypass adversarial defense mechanisms in software neural networks but trigger non-trivial performance discrepancies in ReRAM-based neural networks. To this end, we have proposed a framework to generate adversarial images in the hypervolume between the two decision boundaries, thereby leveraging non-ideal device behavior for performance detriment. We employ state-of-the-art tools in explainable artificial intelligence to characterize our adversarial image samples, and derive a new metric to quantify susceptibility to adversarial attacks at the pixel and device-levels.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100053"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of TSV bump and redistribution layer on crosstalk delay and power loss","authors":"Shivangi Chandrakar,&nbsp;Deepika Gupta,&nbsp;Manoj Kumar Majumder","doi":"10.1016/j.memori.2023.100040","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100040","url":null,"abstract":"<div><p>The performance of a 3D IC is primarily reliant on the selection of an appropriate bump shape. The most prevalent bump shape (cylindrical) is experiencing substantial stress, power loss and crosstalk issues. TSV bump with a tapered structure have recently attracted considerable attention owing to its low volume fraction and coupling capacitance, that can substantially reduce the stress and crosstalk concerns. An impact of the redistribution layer (RDL), intermetal dielectric and high frequency skin effect are appropriately taken into account for the tapered TSV (<em>T</em>-TSV) with a cylindrical, barrel and tapered bump shape. A mathematical framework of the resistance–inductance–conductance–capacitance (<em>RLGC</em>) structure of the proposed <em>T</em>-TSV have been formulated by effectively considering the coupling, passivation and fringing capacitance of the RDL. In order to benchmark the proposed electrical equivalent circuit, the structural model of the <em>T</em>-TSV is validated against the fabrication based experimental results, and a subsequent analysis have been performed for the stress, crosstalk induced delay, and power loss. The proposed TSV structure is in good agreement with the experimental results with an average deviation of only 2.8%. Furthermore, irrespective of bump height, the tapered bump based <em>T</em>-TSV can effectively reduce the overall crosstalk induced delay, stress, power delay product (PDP), insertion and reflection losses with an average deviation of 20.22%, 22.30%, 23.55%, 8.01%, and 10.32%, respectively, when compared to the barrel and cylindrical bumps. In addition, it has been observed that the overall rate of change in PDP, power losses and crosstalk induced delay with considering RDL are 18.8%, 20.50%, and 25.22%, respectively independent of the bump shapes.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100040"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tutorial on memristor-based computing for smart edge applications","authors":"Anteneh Gebregiorgis ,&nbsp;Abhairaj Singh ,&nbsp;Amirreza Yousefzadeh ,&nbsp;Dirk Wouters ,&nbsp;Rajendra Bishnoi ,&nbsp;Francky Catthoor ,&nbsp;Said Hamdioui","doi":"10.1016/j.memori.2023.100025","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100025","url":null,"abstract":"<div><p>Smart computing on edge-devices has demonstrated huge potential for various application sectors such as personalized healthcare and smart robotics. These devices aim at bringing smart computing close to the source where the data is generated or stored, while coping with the stringent resource budget of the edge platforms. The conventional Von-Neumann architecture fails to meet these requirements due to various limitations e.g., the memory-processor data transfer bottleneck. Memristor-based Computation-In-Memory (CIM) has the potential to realize such smart edge computing for data-dominated Artificial Intelligence (AI) applications by exploiting both the inherent properties of the architecture and the physical characteristics of the memristors. This paper discusses different aspects of CIM, including classification, working principle, CIM potentials and CIM design-flow. The design-flow is illustrated through two case studies to demonstrate the huge potential of CIM in realizing orders of magnitude improvement in energy-efficiency as compared to the conventional architectures. Finally future challenges and research directions of CIM are covered.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100025"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Controlling the beam angle spread of carbon implantation for improvement of bin map defect in V-NAND flash memory","authors":"Gui-Fu Yang ,&nbsp;Sung-Hwan Jang ,&nbsp;SUNG-UK JANG ,&nbsp;Tae-Hyun Lee ,&nbsp;Da-Hye Kim ,&nbsp;Jung-Ho Huh ,&nbsp;Seok-Hyun Yoo","doi":"10.1016/j.memori.2023.100027","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100027","url":null,"abstract":"<div><p>As the shrinkage of devices accelerates and the vertical layers increase, beam angle spread of carbon ion implantation (C IIP) for the silicon selective epitaxial growth (Si-SEG) areas in V-NAND is one of the most critical parameters related with bin map defects. The roles of C IIP in Si-SEGs are that it can suppress channeling effect of boron IIP and diffusion limitation of boron dopants during subsequent annealing processes. In this study, beam angle spread was reduced by 36% and the center-to-edge beam angle skew of wafer was reduced to less than 1° by optimizing the specification of tracking magnet and the beam angle mean. After applying the improved process conditions and effective interlocks, the bin defective rate was controlled less than 0.5% successfully.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100027"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust PID controllers tuning based on the beetle antennae search algorithm","authors":"Spyridon D. Mourtas ,&nbsp;Chrysostomos Kasimis ,&nbsp;Vasilios N. Katsikis","doi":"10.1016/j.memori.2023.100030","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100030","url":null,"abstract":"<div><p>The core components of both traditional and contemporary control systems are the proportional–integral–derivative (PID) control systems, which have established themselves as standards for technical and industrial applications. Therefore, the tuning of the PID controllers is of high importance. Utilizing optimization algorithms to reduce the mean square error of the controller’s output is one approach of tuning PID controllers. In this paper, an appropriately modified metaheuristic optimization algorithm dubbed beetle antennae search (BAS) is employed for robust tuning of PID controllers. The findings of three simulated experiments on stabilizing feedback control systems show that BAS produces comparable or higher performance than three other well-known optimization algorithms while only consuming a tenth of their time.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100030"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully bulk CMOS compatible Key Shape Floating Body Memory (KFBM)","authors":"Masakazu Kakumu,&nbsp;Yisuo Li,&nbsp;Koji Sakui,&nbsp;Nozomu Harada","doi":"10.1016/j.memori.2023.100061","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100061","url":null,"abstract":"<div><p>This paper presents a capacitorless memory cell with bulk CMOS compatibility, consisting of a MOSFET with a virtual floating body formed by the trench. The name Key shape Floating Body Memory (KFBM) is derived from the resemblance of the structure to the shape of an antique key. The carrier concentration in the vertical device beneath the MOSFET results in over more than 5 orders of magnitude of the on–off cell current ratio with off-current less than 100pA/cell. The device achieves a retention time of about 1 s at 85C and over 10 s at 27C all the while maintaining high density and scalability. On the basis of TCAD simulation we have demonstrated high tolerance to disturbance (more than 1000 times with all types of signals), which has been an issue with DRAM memories. KFBM can incorporate both dynamic RAM and flash features.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"4 ","pages":"Article 100061"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}