Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Improvement of low-frequency noise behavior with chloridic precursor materials at ALD process","authors":"Daniel Hessler ,&nbsp;Ricardo Olivo ,&nbsp;Tim Baldauf ,&nbsp;Konrad Seidel ,&nbsp;Raik Hoffmann ,&nbsp;Chaiwon Woo ,&nbsp;Maximilian Lederer ,&nbsp;Yannick Raffel","doi":"10.1016/j.memori.2023.100095","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100095","url":null,"abstract":"<div><p>This article reports an improvement in the low-frequency noise characteristics in hafnium oxide-based (<span><math><msub><mrow><mi>HfO</mi></mrow><mrow><mn>2</mn></mrow></msub></math></span>) field-effect transistors by different precursor materials at ALD process. The Hafniumoxide on the devices were fabricated once with organic precursor materials and once with chloridic precursor materials. The investigation shows an improvement in the noise behavior when using chloridic precursor materials. Regarding the main noise source, which are divided into fluctuation of the number of carriers (<span><math><mrow><mi>Δ</mi><mi>N</mi></mrow></math></span>) and fluctuation of the effective transistor mobility (<span><math><mrow><mi>Δ</mi><mi>μ</mi></mrow></math></span>), the results show that the devices fabricated with organic precursor materials show typical behavior of <span><math><mrow><mi>Δ</mi><mi>N</mi></mrow></math></span> noise, where the devices fabricated with chloridic precursor materials show typical behavior of <span><math><mrow><mi>Δ</mi><mi>μ</mi></mrow></math></span> noise.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100095"},"PeriodicalIF":0.0,"publicationDate":"2023-12-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000725/pdfft?md5=58947606bca8ebe048f808d147e89942&pid=1-s2.0-S2773064623000725-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139108962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A review of crosstalk polymorphic circuits and their scalability","authors":"Md Arif Iqbal ,&nbsp;Srinivas Rahul Sapireddy ,&nbsp;Sumanth Dasari ,&nbsp;Kazi Asifuzzaman ,&nbsp;Mostafizur Rahman","doi":"10.1016/j.memori.2023.100094","DOIUrl":"10.1016/j.memori.2023.100094","url":null,"abstract":"<div><p>Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100094"},"PeriodicalIF":0.0,"publicationDate":"2023-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000713/pdfft?md5=1056c6a10ea161086dadba57ae79ee67&pid=1-s2.0-S2773064623000713-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138989702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of heavy ions on a-Si:H/PolySi bilayer thin film transistors with Schottky barrier source and drain based on Nickel Silicide","authors":"Deepak K. Sharma ,&nbsp;Vivek Kumar","doi":"10.1016/j.memori.2023.100096","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100096","url":null,"abstract":"<div><p>This study investigates the influence of heavy ion irradiation on thin film transistors (TFTs) based on an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. Through the use of Technology Computer-Aided Design (TCAD) simulations, we analyze the impact on device performance. We examine the ambipolar device characteristics by varying the thickness of the active layer (Poly-Si) and studying the corresponding physics. Our results reveal that reducing the active layer thickness from 140 to 80 nm decreases the magnitude of the threshold voltage (|VT|) for both nMOS and pMOS operating voltages. Additionally, the subthreshold slope is reduced for both nMOS and pMOS as the active layer thickness is decreased from 140 to 80 nm.</p><p>Further, we investigated the transient response of the drain current to heavy ion irradiation in the sensitive regions across the Schottky barrier-based source and drain. We specifically analyze the phenomenon of bipolar amplification for various Linear Energy Transfer (LET) values, ranging from 0.1 MeV cm²/mg to 100 MeV cm²/mg. Our findings indicate that increasing the LET values from 0.1 MeV cm²/mg to 100 MeV cm²/mg results in amplified bipolar behavior and a drain current overshoot of over 10 % for both pMOS and nMOS operating voltages. To summarize, this work highlights the effects of heavy ion irradiation on TFTs with an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. The study explores the influence of active layer thickness on device characteristics and demonstrates the transient response of drain current under different LET values. These findings contribute to a better understanding of the behavior and performance of TFTs subjected to heavy ion irradiation.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100096"},"PeriodicalIF":0.0,"publicationDate":"2023-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000737/pdfft?md5=1ed0b4079b1ec347280b2404a4f3eebd&pid=1-s2.0-S2773064623000737-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138769892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advancements in metalloid anodes (Si/Ge/B) for air batteries","authors":"Jyotisman Rath ,&nbsp;Brindha Ramasubramanian ,&nbsp;Seeram Ramakrishna ,&nbsp;Vijila Chellappan","doi":"10.1016/j.memori.2023.100097","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100097","url":null,"abstract":"<div><p>Metal-air batteries (MABs) have emerged as a promising contender in the quest for alternative energy storage technologies, rivalling the widespread utilization of lithium-ion batteries (LIBs). Their comparable theoretical energy density to gasoline, reaching ∼12,000 Wh/kg, has sparked great interest. However, the practical implementation of MABs has been hindered by limitations associated with metal anodes, including volume expansion and unwanted side reactions. Surprisingly, the exploration of metalloid-air batteries (MLAB) remains largely unexplored. This comprehensive review aims to shed light on the potential of MLABs as a novel alternative battery technology. This technology employs metalloids in their elemental form or as compounds/alloys. Elemental metalloids, such as Silicon and Germanium, when used as anodes in combination with alkaline or Ionic liquid electrolytes, have showcased remarkable performance, surpassing their metallic counterparts in energy density, corrosiveness, and discharge time, among other critical factors. Moreover, this review delves into the discussion of Borides and Silicides, compounds of elemental Boron and Silicon, respectively, as anode materials for air batteries. Furthermore, diverse metalloid composites and computational studies exploring innovative configurations have also been examined and discussed, paving the way for future advancements in MLABs.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100097"},"PeriodicalIF":0.0,"publicationDate":"2023-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000749/pdfft?md5=66fdb5abec096c8584b98a7e0da50ccb&pid=1-s2.0-S2773064623000749-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138656389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recycling folded cascode two-stage CMOS amplifier","authors":"Ilghar Rezaei ,&nbsp;Ali Soldoozy ,&nbsp;Masoud Soltani Zanjani ,&nbsp;Toktam Aghaee","doi":"10.1016/j.memori.2023.100093","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100093","url":null,"abstract":"<div><p>In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V. The first stage of the circuit utilizes a supper recycling folded cascode design, while the second stage employs a simple cascode amplifier. Additionally, we have utilized a small 1 pF Miller capacitor to stabilize the amplifier response. Based on simulation results, the proposed amplifier demonstrates a DC gain of 110 dB, GBW of 15 MHz, and power consumption of 359 μW. Finally, we conducted Monte Carlo simulations to verify the robustness of the proposed circuit against the process, temperature, supply voltage, and device dimension mismatch variations.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100093"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000701/pdfft?md5=be1d3ee15b782f49d3f665d84c87266d&pid=1-s2.0-S2773064623000701-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138489797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A soft error upset hardened 12T-SRAM cell for space and terrestrial applications","authors":"Pavan Kumar Mukku,&nbsp;Rohit Lorenzo","doi":"10.1016/j.memori.2023.100092","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100092","url":null,"abstract":"<div><p>Various charged particles in space, including alpha particles, neutrons, heavy ions, and photons, pose reliability and stability concerns for memory circuits. These particles also create an ion track in the memory chip, disrupting the storage bit. The standard 6T SRAM is particularly susceptible to these disturbances. Several researchers suggest employing radiation-hardened SRAM cells to solve this problem. Most studies examine the inclusion of redundant nodes in the memory cell to recover the lost bit. This paper shows a new SEUH-12T SRAM memory cell with redundant nodes to deal with the soft error problem. The proposed SEUH-12T memory cell performance is compared to that of reliable radiation-hardened memory cells such as Quatro-10T, We-Quatro-12T, QCCS-12T, STS-10T, RHMC-12T, and RHWC-12T. The proposed SEUH-12T cell protects against single and multiple node disruptions by considering minimum sensitive nodes layout area separation concept. Furthermore, proposed SEUH-12T exhibits 8.5<span><math><mo>×</mo></math></span>/ 6.3<span><math><mo>×</mo></math></span>/ 5.6<span><math><mo>×</mo></math></span>/ 1.4<span><math><mo>×</mo></math></span>/ 1.2<span><math><mo>×</mo></math></span>/ 1.4<span><math><mo>×</mo></math></span>/ 1.04<span><math><mo>×</mo></math></span> times greater read stability than existing 6T-SRAM/ Quatro-10T/ We-Quatro-12T/ QCCS-12T/ STS-10T/ RHMC-12T/ RHWC-12T memory cells.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100092"},"PeriodicalIF":0.0,"publicationDate":"2023-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000695/pdfft?md5=b8d8b45fd53bbf7492079b861f851b8e&pid=1-s2.0-S2773064623000695-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138136196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel simulator designed for grounded negative inductance with lossless characteristics incorporated with single OTRA","authors":"Khushi Banerjee ,&nbsp;Mourina Ghosh ,&nbsp;Chittajit Sarkar ,&nbsp;Sajal Biring","doi":"10.1016/j.memori.2023.100089","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100089","url":null,"abstract":"<div><p>This article introduces a novel design of a simulator for grounded lossless negative inductance by using an active element -single Operational Trans Resistance Amplifier (OTRA) and four passive components. Without interrupting the condition of realization of inductance, the value of the simulated inductance can be independently administered by a MOS based resistor. For validation of the analytical elucidation PSPICE simulation results are used. Moreover, sensitivity analysis, Monte-Carlo simulation, temperature analysis, and % of total harmonic distortion (%THD) are also investigated to verify the functionality of the proposed circuit. As an application claim of the projected configuration, an inductance nullification circuit is also implemented that exposes that the proposed negative inductance simulator may be used to cancel or reduce the effective inductance in a circuit. The Analog Design Environment tool of Cadence Virtuoso is employed for designing the layout of the OTRA.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100089"},"PeriodicalIF":0.0,"publicationDate":"2023-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S277306462300066X/pdfft?md5=7a8ee545dc3e2ddfa4e0428da5f0e514&pid=1-s2.0-S277306462300066X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91987848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An experimental comparison of interface trap density in hafnium oxide-based FeFETs","authors":"Chaiwon Woo ,&nbsp;Yannick Raffel ,&nbsp;Ricardo Olivo ,&nbsp;Konrad Seidel ,&nbsp;Aleksander Gurlo","doi":"10.1016/j.memori.2023.100091","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100091","url":null,"abstract":"<div><p>In recent years, there has been significant progress in the development of high-<span><math><mi>κ</mi></math></span> materials in the semiconductor industry. Given that the contact between the channel and the electrode has a crucial impact on reliability, the selection of electrode materials and their deposition technology is an area that requires extensive research. Additionally, interface trap density has long played a critical role in determining the reliability of field-effect transistors (FETs). Therefore, this paper presents the results of interface trap density in high-<span><math><mi>κ</mi></math></span> FETs obtained using 2-level and 3-level charge pumping methods. Measurements were conducted on a 10 nm oxide thickness n-doped silicon substrate using native k materials such as silicon and zirconium-doped hafnium oxide. The results demonstrate that chlorine-based HfO2 oxide with zirconium doping exhibits the lowest interface defects.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100091"},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000683/pdfft?md5=403632a3438b0e26810f7c2add452f42&pid=1-s2.0-S2773064623000683-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92122566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Circuit simulation of floating-gate FET (FGFET) for logic application","authors":"Yunjae Kim ,&nbsp;Hyoungsoo Kim ,&nbsp;Jongwook Jeon ,&nbsp;Seungjae Baik ,&nbsp;Myounggon Kang","doi":"10.1016/j.memori.2023.100090","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100090","url":null,"abstract":"<div><p>In this study, a floating-gate field-effect transistor (FGFET) structure is proposed and verified through simulations. Current memory devices often rely on the von Neumann architecture which suffers from von Neumann bottleneck. The proposed FGFET is not vulnerable to the von Neumann bottleneck because the memory cell and process unit do not function separately. FGFET is composed with Sensor FET(SFET) and Vertical FET(VFET), which can form a memory node with connection of each part. Moreover, the advantage of FGFET is that the conventional CMOS process can be used. In this regard, the developed FGFET using the existing CMOS process shows that the circuit size, power consumption, and operation delay are significantly reduced compared to a conventional logic circuit. Furthermore, various circuit simulations comprising the proposed FGFET, such as an inverter and NAND/NOR gate, are performed, highlighting the advantages of the proposed FGFET. This study lays the foundation for using a CMOS-based memory logic integrated device and architecture for alleviating the von Neumann bottleneck.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100090"},"PeriodicalIF":0.0,"publicationDate":"2023-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000671/pdfft?md5=a8771122cbc125b8b210bfa707a1399d&pid=1-s2.0-S2773064623000671-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92115859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bio-inspired artificial synapses: Neuromorphic computing chip engineering with soft biomaterials","authors":"Tanvir Ahmed","doi":"10.1016/j.memori.2023.100088","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100088","url":null,"abstract":"<div><p>In the context of neuromorphic computing chip engineering, this review paper explores the area of bio-inspired artificial synapses with a focus on the incorporation of soft biomaterials. Soft biomaterials, including biocompatible hydrogels and organic polymers, have definite advantages in resembling the soft and dynamic properties of biological synapses. The article gives a general review of neuromorphic computing while emphasizing the shortcomings of traditional von Neumann architectures in terms of emulating the functions of the brain in computing. It highlights the artificial synaptic design concepts, including synaptic plasticity and energy efficiency. Spike-timing-dependent plasticity, synaptic weight modulation, and low-power operation can all be incorporated into these synapses thanks to the use of soft biomaterials. Inkjet printing, self-assembly methods, and electrochemical deposition are only a few of the technical techniques covered in this article for creating artificial synapses that are inspired by biological structures. These methods enable accurate biomaterial patterning and deposition, enabling the construction of complex neural networks on neuromorphic circuits. The research also emphasizes possible uses of bio-inspired artificial synapses in robotics, prosthetics, and cognitive computing. Soft biomaterials' capacity to mimic the synaptic activity of the brain creates new opportunities for effective and clever computing systems. In summary, this review paper succinctly outlines the incorporation of soft biomaterials into artificial synapses that are inspired by biological structures for neuromorphic computing chip fabrication. It analyzes production methods, highlights the value of synaptic plasticity and energy efficiency, and examines prospective applications. The development of new computing paradigms and the creation of extremely effective and brain-like computer systems are both significantly impacted by this research.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100088"},"PeriodicalIF":0.0,"publicationDate":"2023-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}