Memories - Materials, Devices, Circuits and Systems最新文献_第5页

Novel simulator designed for grounded negative inductance with lossless characteristics incorporated with single OTRA 新型接地负电感模拟器设计，具有无损特性，并与单个OTRA相结合

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-11-03 DOI: 10.1016/j.memori.2023.100089

Khushi Banerjee , Mourina Ghosh , Chittajit Sarkar , Sajal Biring

{"title":"Novel simulator designed for grounded negative inductance with lossless characteristics incorporated with single OTRA","authors":"Khushi Banerjee , Mourina Ghosh , Chittajit Sarkar , Sajal Biring","doi":"10.1016/j.memori.2023.100089","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100089","url":null,"abstract":"<div><p>This article introduces a novel design of a simulator for grounded lossless negative inductance by using an active element -single Operational Trans Resistance Amplifier (OTRA) and four passive components. Without interrupting the condition of realization of inductance, the value of the simulated inductance can be independently administered by a MOS based resistor. For validation of the analytical elucidation PSPICE simulation results are used. Moreover, sensitivity analysis, Monte-Carlo simulation, temperature analysis, and % of total harmonic distortion (%THD) are also investigated to verify the functionality of the proposed circuit. As an application claim of the projected configuration, an inductance nullification circuit is also implemented that exposes that the proposed negative inductance simulator may be used to cancel or reduce the effective inductance in a circuit. The Analog Design Environment tool of Cadence Virtuoso is employed for designing the layout of the OTRA.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100089"},"PeriodicalIF":0.0,"publicationDate":"2023-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S277306462300066X/pdfft?md5=7a8ee545dc3e2ddfa4e0428da5f0e514&pid=1-s2.0-S277306462300066X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91987848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An experimental comparison of interface trap density in hafnium oxide-based FeFETs 氧化铪基fet中界面阱密度的实验比较

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-31 DOI: 10.1016/j.memori.2023.100091

Chaiwon Woo , Yannick Raffel , Ricardo Olivo , Konrad Seidel , Aleksander Gurlo

{"title":"An experimental comparison of interface trap density in hafnium oxide-based FeFETs","authors":"Chaiwon Woo , Yannick Raffel , Ricardo Olivo , Konrad Seidel , Aleksander Gurlo","doi":"10.1016/j.memori.2023.100091","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100091","url":null,"abstract":"<div><p>In recent years, there has been significant progress in the development of high-<span><math><mi>κ</mi></math></span> materials in the semiconductor industry. Given that the contact between the channel and the electrode has a crucial impact on reliability, the selection of electrode materials and their deposition technology is an area that requires extensive research. Additionally, interface trap density has long played a critical role in determining the reliability of field-effect transistors (FETs). Therefore, this paper presents the results of interface trap density in high-<span><math><mi>κ</mi></math></span> FETs obtained using 2-level and 3-level charge pumping methods. Measurements were conducted on a 10 nm oxide thickness n-doped silicon substrate using native k materials such as silicon and zirconium-doped hafnium oxide. The results demonstrate that chlorine-based HfO2 oxide with zirconium doping exhibits the lowest interface defects.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100091"},"PeriodicalIF":0.0,"publicationDate":"2023-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000683/pdfft?md5=403632a3438b0e26810f7c2add452f42&pid=1-s2.0-S2773064623000683-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92122566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Circuit simulation of floating-gate FET (FGFET) for logic application 浮栅场效应管(FGFET)电路仿真的逻辑应用

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-20 DOI: 10.1016/j.memori.2023.100090

Yunjae Kim , Hyoungsoo Kim , Jongwook Jeon , Seungjae Baik , Myounggon Kang

{"title":"Circuit simulation of floating-gate FET (FGFET) for logic application","authors":"Yunjae Kim , Hyoungsoo Kim , Jongwook Jeon , Seungjae Baik , Myounggon Kang","doi":"10.1016/j.memori.2023.100090","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100090","url":null,"abstract":"<div><p>In this study, a floating-gate field-effect transistor (FGFET) structure is proposed and verified through simulations. Current memory devices often rely on the von Neumann architecture which suffers from von Neumann bottleneck. The proposed FGFET is not vulnerable to the von Neumann bottleneck because the memory cell and process unit do not function separately. FGFET is composed with Sensor FET(SFET) and Vertical FET(VFET), which can form a memory node with connection of each part. Moreover, the advantage of FGFET is that the conventional CMOS process can be used. In this regard, the developed FGFET using the existing CMOS process shows that the circuit size, power consumption, and operation delay are significantly reduced compared to a conventional logic circuit. Furthermore, various circuit simulations comprising the proposed FGFET, such as an inverter and NAND/NOR gate, are performed, highlighting the advantages of the proposed FGFET. This study lays the foundation for using a CMOS-based memory logic integrated device and architecture for alleviating the von Neumann bottleneck.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100090"},"PeriodicalIF":0.0,"publicationDate":"2023-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000671/pdfft?md5=a8771122cbc125b8b210bfa707a1399d&pid=1-s2.0-S2773064623000671-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92115859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Bio-inspired artificial synapses: Neuromorphic computing chip engineering with soft biomaterials 仿生人工突触：软生物材料的神经形态计算芯片工程

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-18 DOI: 10.1016/j.memori.2023.100088

Tanvir Ahmed

{"title":"Bio-inspired artificial synapses: Neuromorphic computing chip engineering with soft biomaterials","authors":"Tanvir Ahmed","doi":"10.1016/j.memori.2023.100088","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100088","url":null,"abstract":"<div><p>In the context of neuromorphic computing chip engineering, this review paper explores the area of bio-inspired artificial synapses with a focus on the incorporation of soft biomaterials. Soft biomaterials, including biocompatible hydrogels and organic polymers, have definite advantages in resembling the soft and dynamic properties of biological synapses. The article gives a general review of neuromorphic computing while emphasizing the shortcomings of traditional von Neumann architectures in terms of emulating the functions of the brain in computing. It highlights the artificial synaptic design concepts, including synaptic plasticity and energy efficiency. Spike-timing-dependent plasticity, synaptic weight modulation, and low-power operation can all be incorporated into these synapses thanks to the use of soft biomaterials. Inkjet printing, self-assembly methods, and electrochemical deposition are only a few of the technical techniques covered in this article for creating artificial synapses that are inspired by biological structures. These methods enable accurate biomaterial patterning and deposition, enabling the construction of complex neural networks on neuromorphic circuits. The research also emphasizes possible uses of bio-inspired artificial synapses in robotics, prosthetics, and cognitive computing. Soft biomaterials' capacity to mimic the synaptic activity of the brain creates new opportunities for effective and clever computing systems. In summary, this review paper succinctly outlines the incorporation of soft biomaterials into artificial synapses that are inspired by biological structures for neuromorphic computing chip fabrication. It analyzes production methods, highlights the value of synaptic plasticity and energy efficiency, and examines prospective applications. The development of new computing paradigms and the creation of extremely effective and brain-like computer systems are both significantly impacted by this research.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100088"},"PeriodicalIF":0.0,"publicationDate":"2023-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Building an IoT temperature and humidity forecasting model based on long short-term memory (LSTM) with improved whale optimization algorithm 利用改进的whale优化算法构建基于长短期记忆（LSTM）的物联网温湿度预测模型

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-13 DOI: 10.1016/j.memori.2023.100086

Mustafa Wassef Hasan

{"title":"Building an IoT temperature and humidity forecasting model based on long short-term memory (LSTM) with improved whale optimization algorithm","authors":"Mustafa Wassef Hasan","doi":"10.1016/j.memori.2023.100086","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100086","url":null,"abstract":"<div><p>In particular, predicting the temperature and humidity information plays a crucial role in plantation, estimating rainfalls and climate change, and predicting air quality via specified geographical regions. The temperature and humidity forecasting information is occasionally presented with low accuracy due to uncertain techniques and vast methods that employ different sensors and models. For this reason, this work proposes an Internet of Things (IoT) temperature and humidity forecasting model based on an improved whale optimization algorithm with long short-term memory (IWOA-LSTM) technique. To increase the convergence speed processing time and overcome the local optimization problem, the IWOA is introduced. The number of hidden layers, learning rate momentum, and weight decay of the LSTM optimized using the IWOA. The actual temperature and humidity data are collected using DHT11 and ESP8266 NodeMCU practical model and processed using the ThingSpeak platform. The processing data stage depends on filling the missing data gaps using the rolling average technique (RAT). The performance evaluation of the proposed IWOA-LSTM forecasting model is assessed using some statistical functions, namely known as mean square error, mean absolute error, root mean square error, and mean absolute percentage error. The IWOA-LSTM techniques were also assessed using throughput, latency, and power consumption. The developed IWOA-LSTM model shows high accuracy, leading to better forecasting information than other forecasting models.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100086"},"PeriodicalIF":0.0,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Structural, optical, and electrical characteristics of Ge18Bi4Se78 chalcogenide glass for optoelectronic applications 用于光电子应用的Ge18Bi4Se78硫族化物玻璃的结构、光学和电学特性

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-12 DOI: 10.1016/j.memori.2023.100085

S.K. Mohamed, M.M. Abd El-Raheem, M.M. Wakkad, A.M. Abdel Hakeeam, H.F. Mohamed

{"title":"Structural, optical, and electrical characteristics of Ge18Bi4Se78 chalcogenide glass for optoelectronic applications","authors":"S.K. Mohamed, M.M. Abd El-Raheem, M.M. Wakkad, A.M. Abdel Hakeeam, H.F. Mohamed","doi":"10.1016/j.memori.2023.100085","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100085","url":null,"abstract":"<div><p>The melt quenching and thermal evaporation techniques were used to produce the chalcogenide glass Ge<sub>18</sub>Bi<sub>4</sub>Se<sub>78</sub> powder and thin film samples, respectively. The as-deposited and annealed thin films at (180, 200, 300, 320 °C) are characterized by X-ray diffractometer and scanning electron microscopy. The Urbach tail energy E<sub>u</sub> and the optical energy gap E<sub>op</sub> are investigated. As well, the Swanepoel method revealed that the refractive index exhibited normal dispersion behavior. In addition, the single oscillator, dispersion energies, the lattice dielectric constant, <span><math><mrow><msub><mi>ε</mi><mi>L</mi></msub></mrow></math></span>, plasma frequency, <span><math><mrow><msub><mi>ω</mi><mi>p</mi></msub></mrow></math></span>, and optical conductivity, <span><math><mrow><msub><mi>σ</mi><mrow><mi>o</mi><mi>p</mi></mrow></msub></mrow></math></span> were all examined. The electrical conductivity and the activation energies for as-deposited and annealed thin films were calculated. Whereas the J-E properties of the as-deposited and annealed films indicated varied ranges of negative differential conductance NDC depending on the annealing temperatures.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100085"},"PeriodicalIF":0.0,"publicationDate":"2023-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network 用电路理论和分析米勒补偿网络设计三级CMOS放大器

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-12 DOI: 10.1016/j.memori.2023.100084

Ilghar Rezaei , Ali Soldoozy , Amir Ali Mohammad Khani , Ali Biabanifard

引用次数: 1

Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications 用于存储电路应用的无连接双栅沟槽沟道（JL-TGTC）MOSFET的数字逻辑评估

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-11 DOI: 10.1016/j.memori.2023.100087

Ajay Kumar , Neha Gupta , Aditya Jain , Rajeev Gupta , Bharat Choudhary , Kaushal Kumar , Amit Kumar Goyal , Yehia Massoud

引用次数: 0

A study of ZnO doped PDMS towards boosting of triboelectric energy harvester performance ZnO掺杂PDMS提高摩擦电能采集器性能的研究

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-07 DOI: 10.1016/j.memori.2023.100082

Hitesh Kr Sharma , Vijay Janyani , D. Boolchandani , Atul Kr Sharma

{"title":"A study of ZnO doped PDMS towards boosting of triboelectric energy harvester performance","authors":"Hitesh Kr Sharma , Vijay Janyani , D. Boolchandani , Atul Kr Sharma","doi":"10.1016/j.memori.2023.100082","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100082","url":null,"abstract":"<div><p>In this article, a study of ZnO doping in poly-dimethyl-siloxane (PDMS) polymer, which is used as one tribo layer in tribo-electric energy harvesters (TEG) is corroborated to enhance the electrical properties, open circuit voltage (V<sub>oc</sub>)and short circuit current (I<sub>SC</sub>). A parallel plate device configuration of metal-to-dielectric approach is carried out making use of copper as metal and PDMS polymer with ZnO doping as a dielectric film. The double sided copper tape of 99.99 % purity and 60 μm thickness is used to realize the top tribo layer whiledielectric PDMS polymer film with ZnO doping of 8 wt%, 13 wt%, and 18 wt% is spin coated at 1000 rpm on single side copper coated FR4 substrate to make the bottom tribo-electic layer. The mechanical force is applied in tapping mode on top layer by Universal Testing Machine (UTM). The prototype device is characterized by Agilent DSO, which revealed peak output voltage of 15 V, 20 V, 30 V, and 41 V and peak-to-peak output voltage 38 V, 50 V, 60 V, and 69 V in pure PDMS, PDMS+8 % ZnO, PDMS+13 % ZnO, and PDMS+18 % ZnO respectively. The output peak current is obtained 9 nA, 20 nA, 30 nA, and 32 nA and peak-to-peak current 31 nA, 49 nA, 51 nA, and 60 nA respectively. The performance of ZnO doped PDMS TEG has increased adequately, up to 68.44 % Of V<sub>oc</sub> and 71.87 % of I<sub>sc.</sub>with respect to pure PDMS. A scanning electron microscope (SEM) is used to confirm polymer film morphology and ZnO doping percentage in PDMS is validatedby energy dispersive X-ray spectroscopy.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100082"},"PeriodicalIF":0.0,"publicationDate":"2023-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide 考虑高k栅氧化物对SOI基GaN FinFET直流和模拟/RF性能的影响

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-01 DOI: 10.1016/j.memori.2023.100079

Vandana Singh Rajawat , Ajay Kumar , Bharat Choudhary

{"title":"Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide","authors":"Vandana Singh Rajawat , Ajay Kumar , Bharat Choudhary","doi":"10.1016/j.memori.2023.100079","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100079","url":null,"abstract":"<div><p>This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence band energy, and subthreshold swing is reported. All these parameters are analyzed and compared with bulk GaN FinFET and Si FinFET. We achieve better ON current, faster speed, and more minor subthreshold swing, reducing the short channel effects. A shallow OFF current is obtained because of bulk conduction in the GaN channel area, which the gate can deplete. Several RF/analog metrics are also noted, including transconductance (g<sub>m</sub>), cut-off frequency (f<sub>T</sub>), transconductance frequency product (TFP), and transconductance generation factor (TGF), and comparison with Bulk GaN FinFET and Si FinFET is presented. Finally, the linearity metrics like 2nd and 3rd-order voltage intercept points, IIP3, and 1-dB compression point is extracted. Compared to the other two structures, the suggested structure exhibits advantageous DC and RF/analog performances. A comparison of different Figures of Merits (FoMs) for the suggested device with previously published literature is also given.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100079"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50193735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0