Memories - Materials, Devices, Circuits and Systems最新文献

{"title":"Improvement of low-frequency noise behavior with chloridic precursor materials at ALD process","authors":"Daniel Hessler ,&nbsp;Ricardo Olivo ,&nbsp;Tim Baldauf ,&nbsp;Konrad Seidel ,&nbsp;Raik Hoffmann ,&nbsp;Chaiwon Woo ,&nbsp;Maximilian Lederer ,&nbsp;Yannick Raffel","doi":"10.1016/j.memori.2023.100095","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100095","url":null,"abstract":"<div><p>This article reports an improvement in the low-frequency noise characteristics in hafnium oxide-based (<span><math><msub><mrow><mi>HfO</mi></mrow><mrow><mn>2</mn></mrow></msub></math></span>) field-effect transistors by different precursor materials at ALD process. The Hafniumoxide on the devices were fabricated once with organic precursor materials and once with chloridic precursor materials. The investigation shows an improvement in the noise behavior when using chloridic precursor materials. Regarding the main noise source, which are divided into fluctuation of the number of carriers (<span><math><mrow><mi>Δ</mi><mi>N</mi></mrow></math></span>) and fluctuation of the effective transistor mobility (<span><math><mrow><mi>Δ</mi><mi>μ</mi></mrow></math></span>), the results show that the devices fabricated with organic precursor materials show typical behavior of <span><math><mrow><mi>Δ</mi><mi>N</mi></mrow></math></span> noise, where the devices fabricated with chloridic precursor materials show typical behavior of <span><math><mrow><mi>Δ</mi><mi>μ</mi></mrow></math></span> noise.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100095"},"PeriodicalIF":0.0,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000725/pdfft?md5=58947606bca8ebe048f808d147e89942&pid=1-s2.0-S2773064623000725-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139108962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Meta-surface filter for visible frequency range based on meta-materials","authors":"Ali Soldoozy ,&nbsp;Ilghar Rezaei ,&nbsp;Masoud Soltani Zanjani ,&nbsp;Hassan Sadrnia","doi":"10.1016/j.memori.2023.100098","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100098","url":null,"abstract":"<div><p>To enhance the efficiency of exposure in greenhouses during specific cultivation periods, it is essential to design a meta-face that effectively filters the green part of visible light. This targeted filtering function will enable optimal control of the light spectrum, resulting in better cultivation conditions and increased productivity. Leveraging innovative concepts and advanced methods, a highly efficient meta-surface design aimed at filtering the green portion of the visible light spectrum is proposed. The proposed structure comprises periodic arrays of graphene disks and rings strategically positioned on both sides of a silicon oxide substrate. This straightforward coated layer configuration offers a practical solution for greenhouses and controlled agriculture applications, facilitating improved light management and tailored growth conditions. Through two separate simulation paths, the validity and accuracy of our proposed approach were investigated. Both theoretical analysis and simulation results demonstrate that the proposed structure attenuates the green part of visible light. Filtered output waves prove to be highly beneficial for indoor cultivation, during the flowering period, offering improved control over light conditions. The design methodology relies on an equivalent circuit model and impedance matching criteria. Additionally, full-wave simulation is performed to verify the effectiveness of the employed modeling. According to the simulation results, the proposed meta-surface effectively filters the green part of visible light, while allowing the transmission of the red spectrum.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100098"},"PeriodicalIF":0.0,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000750/pdfft?md5=f5bd87a4fd99884caf1be7a7121db578&pid=1-s2.0-S2773064623000750-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139108963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A review of crosstalk polymorphic circuits and their scalability","authors":"Md Arif Iqbal ,&nbsp;Srinivas Rahul Sapireddy ,&nbsp;Sumanth Dasari ,&nbsp;Kazi Asifuzzaman ,&nbsp;Mostafizur Rahman","doi":"10.1016/j.memori.2023.100094","DOIUrl":"10.1016/j.memori.2023.100094","url":null,"abstract":"<div><p>Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"7 ","pages":"Article 100094"},"PeriodicalIF":0.0,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000713/pdfft?md5=1056c6a10ea161086dadba57ae79ee67&pid=1-s2.0-S2773064623000713-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138989702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Structural, optical, and electrical characteristics of Ge18Bi4Se78 chalcogenide glass for optoelectronic applications","authors":"S.K. Mohamed,&nbsp;M.M. Abd El-Raheem,&nbsp;M.M. Wakkad,&nbsp;A.M. Abdel Hakeeam,&nbsp;H.F. Mohamed","doi":"10.1016/j.memori.2023.100085","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100085","url":null,"abstract":"<div><p>The melt quenching and thermal evaporation techniques were used to produce the chalcogenide glass Ge₁₈Bi₄Se₇₈ powder and thin film samples, respectively. The as-deposited and annealed thin films at (180, 200, 300, 320 °C) are characterized by X-ray diffractometer and scanning electron microscopy. The Urbach tail energy E_u and the optical energy gap E_op are investigated. As well, the Swanepoel method revealed that the refractive index exhibited normal dispersion behavior. In addition, the single oscillator, dispersion energies, the lattice dielectric constant, <span><math><mrow><msub><mi>ε</mi><mi>L</mi></msub></mrow></math></span>, plasma frequency, <span><math><mrow><msub><mi>ω</mi><mi>p</mi></msub></mrow></math></span>, and optical conductivity, <span><math><mrow><msub><mi>σ</mi><mrow><mi>o</mi><mi>p</mi></mrow></msub></mrow></math></span> were all examined. The electrical conductivity and the activation energies for as-deposited and annealed thin films were calculated. Whereas the J-E properties of the as-deposited and annealed films indicated varied ranges of negative differential conductance NDC depending on the annealing temperatures.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100085"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bio-inspired artificial synapses: Neuromorphic computing chip engineering with soft biomaterials","authors":"Tanvir Ahmed","doi":"10.1016/j.memori.2023.100088","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100088","url":null,"abstract":"<div><p>In the context of neuromorphic computing chip engineering, this review paper explores the area of bio-inspired artificial synapses with a focus on the incorporation of soft biomaterials. Soft biomaterials, including biocompatible hydrogels and organic polymers, have definite advantages in resembling the soft and dynamic properties of biological synapses. The article gives a general review of neuromorphic computing while emphasizing the shortcomings of traditional von Neumann architectures in terms of emulating the functions of the brain in computing. It highlights the artificial synaptic design concepts, including synaptic plasticity and energy efficiency. Spike-timing-dependent plasticity, synaptic weight modulation, and low-power operation can all be incorporated into these synapses thanks to the use of soft biomaterials. Inkjet printing, self-assembly methods, and electrochemical deposition are only a few of the technical techniques covered in this article for creating artificial synapses that are inspired by biological structures. These methods enable accurate biomaterial patterning and deposition, enabling the construction of complex neural networks on neuromorphic circuits. The research also emphasizes possible uses of bio-inspired artificial synapses in robotics, prosthetics, and cognitive computing. Soft biomaterials' capacity to mimic the synaptic activity of the brain creates new opportunities for effective and clever computing systems. In summary, this review paper succinctly outlines the incorporation of soft biomaterials into artificial synapses that are inspired by biological structures for neuromorphic computing chip fabrication. It analyzes production methods, highlights the value of synaptic plasticity and energy efficiency, and examines prospective applications. The development of new computing paradigms and the creation of extremely effective and brain-like computer systems are both significantly impacted by this research.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100088"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications","authors":"Ajay Kumar ,&nbsp;Neha Gupta ,&nbsp;Aditya Jain ,&nbsp;Rajeev Gupta ,&nbsp;Bharat Choudhary ,&nbsp;Kaushal Kumar ,&nbsp;Amit Kumar Goyal ,&nbsp;Yehia Massoud","doi":"10.1016/j.memori.2023.100087","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100087","url":null,"abstract":"<div><p>In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100087"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel simulator designed for grounded negative inductance with lossless characteristics incorporated with single OTRA","authors":"Khushi Banerjee ,&nbsp;Mourina Ghosh ,&nbsp;Chittajit Sarkar ,&nbsp;Sajal Biring","doi":"10.1016/j.memori.2023.100089","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100089","url":null,"abstract":"<div><p>This article introduces a novel design of a simulator for grounded lossless negative inductance by using an active element -single Operational Trans Resistance Amplifier (OTRA) and four passive components. Without interrupting the condition of realization of inductance, the value of the simulated inductance can be independently administered by a MOS based resistor. For validation of the analytical elucidation PSPICE simulation results are used. Moreover, sensitivity analysis, Monte-Carlo simulation, temperature analysis, and % of total harmonic distortion (%THD) are also investigated to verify the functionality of the proposed circuit. As an application claim of the projected configuration, an inductance nullification circuit is also implemented that exposes that the proposed negative inductance simulator may be used to cancel or reduce the effective inductance in a circuit. The Analog Design Environment tool of Cadence Virtuoso is employed for designing the layout of the OTRA.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100089"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S277306462300066X/pdfft?md5=7a8ee545dc3e2ddfa4e0428da5f0e514&pid=1-s2.0-S277306462300066X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91987848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network","authors":"Ilghar Rezaei ,&nbsp;Ali Soldoozy ,&nbsp;Amir Ali Mohammad Khani ,&nbsp;Ali Biabanifard","doi":"10.1016/j.memori.2023.100084","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100084","url":null,"abstract":"<div><p>This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100084"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An experimental comparison of interface trap density in hafnium oxide-based FeFETs","authors":"Chaiwon Woo ,&nbsp;Yannick Raffel ,&nbsp;Ricardo Olivo ,&nbsp;Konrad Seidel ,&nbsp;Aleksander Gurlo","doi":"10.1016/j.memori.2023.100091","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100091","url":null,"abstract":"<div><p>In recent years, there has been significant progress in the development of high-<span><math><mi>κ</mi></math></span> materials in the semiconductor industry. Given that the contact between the channel and the electrode has a crucial impact on reliability, the selection of electrode materials and their deposition technology is an area that requires extensive research. Additionally, interface trap density has long played a critical role in determining the reliability of field-effect transistors (FETs). Therefore, this paper presents the results of interface trap density in high-<span><math><mi>κ</mi></math></span> FETs obtained using 2-level and 3-level charge pumping methods. Measurements were conducted on a 10 nm oxide thickness n-doped silicon substrate using native k materials such as silicon and zirconium-doped hafnium oxide. The results demonstrate that chlorine-based HfO2 oxide with zirconium doping exhibits the lowest interface defects.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100091"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000683/pdfft?md5=403632a3438b0e26810f7c2add452f42&pid=1-s2.0-S2773064623000683-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92122566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recycling folded cascode two-stage CMOS amplifier","authors":"Ilghar Rezaei ,&nbsp;Ali Soldoozy ,&nbsp;Masoud Soltani Zanjani ,&nbsp;Toktam Aghaee","doi":"10.1016/j.memori.2023.100093","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100093","url":null,"abstract":"<div><p>In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V. The first stage of the circuit utilizes a supper recycling folded cascode design, while the second stage employs a simple cascode amplifier. Additionally, we have utilized a small 1 pF Miller capacitor to stabilize the amplifier response. Based on simulation results, the proposed amplifier demonstrates a DC gain of 110 dB, GBW of 15 MHz, and power consumption of 359 μW. Finally, we conducted Monte Carlo simulations to verify the robustness of the proposed circuit against the process, temperature, supply voltage, and device dimension mismatch variations.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100093"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000701/pdfft?md5=be1d3ee15b782f49d3f665d84c87266d&pid=1-s2.0-S2773064623000701-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138489797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}