{"title":"Building an IoT temperature and humidity forecasting model based on long short-term memory (LSTM) with improved whale optimization algorithm","authors":"Mustafa Wassef Hasan","doi":"10.1016/j.memori.2023.100086","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100086","url":null,"abstract":"<div><p>In particular, predicting the temperature and humidity information plays a crucial role in plantation, estimating rainfalls and climate change, and predicting air quality via specified geographical regions. The temperature and humidity forecasting information is occasionally presented with low accuracy due to uncertain techniques and vast methods that employ different sensors and models. For this reason, this work proposes an Internet of Things (IoT) temperature and humidity forecasting model based on an improved whale optimization algorithm with long short-term memory (IWOA-LSTM) technique. To increase the convergence speed processing time and overcome the local optimization problem, the IWOA is introduced. The number of hidden layers, learning rate momentum, and weight decay of the LSTM optimized using the IWOA. The actual temperature and humidity data are collected using DHT11 and ESP8266 NodeMCU practical model and processed using the ThingSpeak platform. The processing data stage depends on filling the missing data gaps using the rolling average technique (RAT). The performance evaluation of the proposed IWOA-LSTM forecasting model is assessed using some statistical functions, namely known as mean square error, mean absolute error, root mean square error, and mean absolute percentage error. The IWOA-LSTM techniques were also assessed using throughput, latency, and power consumption. The developed IWOA-LSTM model shows high accuracy, leading to better forecasting information than other forecasting models.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100086"},"PeriodicalIF":0.0,"publicationDate":"2023-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Structural, optical, and electrical characteristics of Ge18Bi4Se78 chalcogenide glass for optoelectronic applications","authors":"S.K. Mohamed, M.M. Abd El-Raheem, M.M. Wakkad, A.M. Abdel Hakeeam, H.F. Mohamed","doi":"10.1016/j.memori.2023.100085","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100085","url":null,"abstract":"<div><p>The melt quenching and thermal evaporation techniques were used to produce the chalcogenide glass Ge<sub>18</sub>Bi<sub>4</sub>Se<sub>78</sub> powder and thin film samples, respectively. The as-deposited and annealed thin films at (180, 200, 300, 320 °C) are characterized by X-ray diffractometer and scanning electron microscopy. The Urbach tail energy E<sub>u</sub> and the optical energy gap E<sub>op</sub> are investigated. As well, the Swanepoel method revealed that the refractive index exhibited normal dispersion behavior. In addition, the single oscillator, dispersion energies, the lattice dielectric constant, <span><math><mrow><msub><mi>ε</mi><mi>L</mi></msub></mrow></math></span>, plasma frequency, <span><math><mrow><msub><mi>ω</mi><mi>p</mi></msub></mrow></math></span>, and optical conductivity, <span><math><mrow><msub><mi>σ</mi><mrow><mi>o</mi><mi>p</mi></mrow></msub></mrow></math></span> were all examined. The electrical conductivity and the activation energies for as-deposited and annealed thin films were calculated. Whereas the J-E properties of the as-deposited and annealed films indicated varied ranges of negative differential conductance NDC depending on the annealing temperatures.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100085"},"PeriodicalIF":0.0,"publicationDate":"2023-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ilghar Rezaei , Ali Soldoozy , Amir Ali Mohammad Khani , Ali Biabanifard
{"title":"Circuit design of a three-stage CMOS amplifier by circuit theory and analysis miller compensation network","authors":"Ilghar Rezaei , Ali Soldoozy , Amir Ali Mohammad Khani , Ali Biabanifard","doi":"10.1016/j.memori.2023.100084","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100084","url":null,"abstract":"<div><p>This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100084"},"PeriodicalIF":0.0,"publicationDate":"2023-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications","authors":"Ajay Kumar , Neha Gupta , Aditya Jain , Rajeev Gupta , Bharat Choudhary , Kaushal Kumar , Amit Kumar Goyal , Yehia Massoud","doi":"10.1016/j.memori.2023.100087","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100087","url":null,"abstract":"<div><p>In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100087"},"PeriodicalIF":0.0,"publicationDate":"2023-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study of ZnO doped PDMS towards boosting of triboelectric energy harvester performance","authors":"Hitesh Kr Sharma , Vijay Janyani , D. Boolchandani , Atul Kr Sharma","doi":"10.1016/j.memori.2023.100082","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100082","url":null,"abstract":"<div><p>In this article, a study of ZnO doping in poly-dimethyl-siloxane (PDMS) polymer, which is used as one tribo layer in tribo-electric energy harvesters (TEG) is corroborated to enhance the electrical properties, open circuit voltage (V<sub>oc</sub>)and short circuit current (I<sub>SC</sub>). A parallel plate device configuration of metal-to-dielectric approach is carried out making use of copper as metal and PDMS polymer with ZnO doping as a dielectric film. The double sided copper tape of 99.99 % purity and 60 μm thickness is used to realize the top tribo layer whiledielectric PDMS polymer film with ZnO doping of 8 wt%, 13 wt%, and 18 wt% is spin coated at 1000 rpm on single side copper coated FR4 substrate to make the bottom tribo-electic layer. The mechanical force is applied in tapping mode on top layer by Universal Testing Machine (UTM). The prototype device is characterized by Agilent DSO, which revealed peak output voltage of 15 V, 20 V, 30 V, and 41 V and peak-to-peak output voltage 38 V, 50 V, 60 V, and 69 V in pure PDMS, PDMS+8 % ZnO, PDMS+13 % ZnO, and PDMS+18 % ZnO respectively. The output peak current is obtained 9 nA, 20 nA, 30 nA, and 32 nA and peak-to-peak current 31 nA, 49 nA, 51 nA, and 60 nA respectively. The performance of ZnO doped PDMS TEG has increased adequately, up to 68.44 % Of V<sub>oc</sub> and 71.87 % of I<sub>sc.</sub>with respect to pure PDMS. A scanning electron microscope (SEM) is used to confirm polymer film morphology and ZnO doping percentage in PDMS is validatedby energy dispersive X-ray spectroscopy.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100082"},"PeriodicalIF":0.0,"publicationDate":"2023-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide","authors":"Vandana Singh Rajawat , Ajay Kumar , Bharat Choudhary","doi":"10.1016/j.memori.2023.100079","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100079","url":null,"abstract":"<div><p>This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence band energy, and subthreshold swing is reported. All these parameters are analyzed and compared with bulk GaN FinFET and Si FinFET. We achieve better ON current, faster speed, and more minor subthreshold swing, reducing the short channel effects. A shallow OFF current is obtained because of bulk conduction in the GaN channel area, which the gate can deplete. Several RF/analog metrics are also noted, including transconductance (g<sub>m</sub>), cut-off frequency (f<sub>T</sub>), transconductance frequency product (TFP), and transconductance generation factor (TGF), and comparison with Bulk GaN FinFET and Si FinFET is presented. Finally, the linearity metrics like 2nd and 3rd-order voltage intercept points, IIP3, and 1-dB compression point is extracted. Compared to the other two structures, the suggested structure exhibits advantageous DC and RF/analog performances. A comparison of different Figures of Merits (FoMs) for the suggested device with previously published literature is also given.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100079"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50193735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Toolflow for the algorithm-hardware co-design of memristive ANN accelerators","authors":"Malte Wabnitz, Tobias Gemmeke","doi":"10.1016/j.memori.2023.100066","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100066","url":null,"abstract":"<div><p>The capabilities of artificial neural networks are rapidly evolving, so are the expectations for them to solve ever more challenging tasks in numerous everyday situations. Larger, more complex networks and the need to execute them efficiently on edge devices are the two counteracting requirements of this trend. Novel devices and computation techniques show promising characteristics to address this challenge. A huge design space covering different combinations of neural networks and hardware architectures using these technologies needs to be explored. An efficient design flow is, therefore, crucial for a good quality of service. This work reviews a wide range of simulation tools for novel memristive devices and analyzes their applicability for the design space exploration. A modular toolflow is proposed that shrinks down the large design space step-by-step using state-of-the-art optimization techniques and builds upon existing tools to find the best trade-offs between network accuracy and hardware requirements.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100066"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50193739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Iulia Salaoru, Swapnodoot Ganguly, Dave Morris, Shashi Paul
{"title":"Materials and challenges of 3D printing of emerging memory devices","authors":"Iulia Salaoru, Swapnodoot Ganguly, Dave Morris, Shashi Paul","doi":"10.1016/j.memori.2023.100067","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100067","url":null,"abstract":"<div><p>The continuous development of the semiconductor industry to meet the increasing demand of modern electronic devices which can enhance computing capabilities is attributed to the exploration of efficient, simple, high-speed operation and multistate information storage capacity of electronic devices called memory devices. Nowadays, one of the main challenges the industry faces is limitations in manufacturing as the current fabrication pathway is complex and relies on the use of rigid substrates that do not match with the needs of industry for flexible, bendable electronics. 3D printing has a huge potential to address this challenge and to completely replace the current fabrication pathways and protocols. In this paper, the materials and the 3D printing technologies that have been explored to fabricate an emerging flexible, bendable memory device will be presented.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100067"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50193741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jae-Min Sim , In-Ku Kang , Sung-In Hong , Changhan Kim , Changhyun Cho , Kyunghoon Min , Yun-Heub Song
{"title":"A novel gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance with disturbance-less program operation","authors":"Jae-Min Sim , In-Ku Kang , Sung-In Hong , Changhan Kim , Changhyun Cho , Kyunghoon Min , Yun-Heub Song","doi":"10.1016/j.memori.2023.100073","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100073","url":null,"abstract":"<div><p>In this paper, we propose a gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance and reliability. First, in the selected string, we confirmed that the proposed structure can improve program performance using negative bit-line voltage scheme with pass disturbance-less characteristic. Second, in the inhibited string, we confirmed self-boosting, which is perfectly performed by the back-gate bias without the unselected WL. Based on these potentials of the GAAB NAND structure, we would like to propose our GAAB structure as a future structure with the advantages of high performance and high reliability characteristics compared with conventional GAA-type NAND flash memory.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100073"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50194261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. A. Md. Monzur-Ul-Akhir , Saiful Islam , Md. Touhidul Imam , Sharnali Islam , Tasnia Hossain , Mohammad Junaebur Rashid
{"title":"Modeling and performance study of CZTS solar cell with novel cupric oxide (CuO) as a bilayer absorber","authors":"A. A. Md. Monzur-Ul-Akhir , Saiful Islam , Md. Touhidul Imam , Sharnali Islam , Tasnia Hossain , Mohammad Junaebur Rashid","doi":"10.1016/j.memori.2023.100083","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100083","url":null,"abstract":"<div><p>A Kesterite material like CZTS provides the steering to the researcher with their tunable bandgap and high optical coefficient above 10<sup>4</sup> cm<sup>−1</sup> for solar cells. These features make it a suitable material for a single junction solar cell increasing the acceptance as well. In this paper, comparative numerical simulations were performed on a regular base structure of CZTS absorber layer with a CdS buffer layer, a ZnO window layer, and a transparent n-ITO conducting layer with a proposed structure where CZTS absorber layer is replaced by a CZTS and CuO bi-layer using SCAPS-1D software to optimize the efficiency. In addition to that the thickness, defect densities and doping concentrations of the absorber layers and temperature were varied to observe the responses of open-circuit voltage (<em>V</em><sub>OC</sub>), short-circuit current (<em>J</em><sub>SC</sub>), fill factor (FF) and efficiency (<em>η</em>) of the solar cell. Among the three basic researchs on lost mechanism for kesterite materials, we have focused on improving the back contact interface recombination through an absorber bi-layer combination of CZTS and CuO resulting in increased V<sub>OC</sub>, Quantum efficiency and carrier generation efficiency approximately by 50 %, 8.94 %, and 34 % respectively, elevating the efficiency of the proposed structure to 19.92 %.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100083"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50194263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}