Memories - Materials, Devices, Circuits and Systems最新文献_第6页

Building an IoT temperature and humidity forecasting model based on long short-term memory (LSTM) with improved whale optimization algorithm 利用改进的whale优化算法构建基于长短期记忆（LSTM）的物联网温湿度预测模型

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-12-01 Epub Date: 2023-10-13 DOI: 10.1016/j.memori.2023.100086

Mustafa Wassef Hasan

{"title":"Building an IoT temperature and humidity forecasting model based on long short-term memory (LSTM) with improved whale optimization algorithm","authors":"Mustafa Wassef Hasan","doi":"10.1016/j.memori.2023.100086","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100086","url":null,"abstract":"<div><p>In particular, predicting the temperature and humidity information plays a crucial role in plantation, estimating rainfalls and climate change, and predicting air quality via specified geographical regions. The temperature and humidity forecasting information is occasionally presented with low accuracy due to uncertain techniques and vast methods that employ different sensors and models. For this reason, this work proposes an Internet of Things (IoT) temperature and humidity forecasting model based on an improved whale optimization algorithm with long short-term memory (IWOA-LSTM) technique. To increase the convergence speed processing time and overcome the local optimization problem, the IWOA is introduced. The number of hidden layers, learning rate momentum, and weight decay of the LSTM optimized using the IWOA. The actual temperature and humidity data are collected using DHT11 and ESP8266 NodeMCU practical model and processed using the ThingSpeak platform. The processing data stage depends on filling the missing data gaps using the rolling average technique (RAT). The performance evaluation of the proposed IWOA-LSTM forecasting model is assessed using some statistical functions, namely known as mean square error, mean absolute error, root mean square error, and mean absolute percentage error. The IWOA-LSTM techniques were also assessed using throughput, latency, and power consumption. The developed IWOA-LSTM model shows high accuracy, leading to better forecasting information than other forecasting models.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100086"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A soft error upset hardened 12T-SRAM cell for space and terrestrial applications 用于空间和地面应用的软错误破坏硬化12T-SRAM单元

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-12-01 Epub Date: 2023-11-20 DOI: 10.1016/j.memori.2023.100092

Pavan Kumar Mukku, Rohit Lorenzo

{"title":"A soft error upset hardened 12T-SRAM cell for space and terrestrial applications","authors":"Pavan Kumar Mukku, Rohit Lorenzo","doi":"10.1016/j.memori.2023.100092","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100092","url":null,"abstract":"<div><p>Various charged particles in space, including alpha particles, neutrons, heavy ions, and photons, pose reliability and stability concerns for memory circuits. These particles also create an ion track in the memory chip, disrupting the storage bit. The standard 6T SRAM is particularly susceptible to these disturbances. Several researchers suggest employing radiation-hardened SRAM cells to solve this problem. Most studies examine the inclusion of redundant nodes in the memory cell to recover the lost bit. This paper shows a new SEUH-12T SRAM memory cell with redundant nodes to deal with the soft error problem. The proposed SEUH-12T memory cell performance is compared to that of reliable radiation-hardened memory cells such as Quatro-10T, We-Quatro-12T, QCCS-12T, STS-10T, RHMC-12T, and RHWC-12T. The proposed SEUH-12T cell protects against single and multiple node disruptions by considering minimum sensitive nodes layout area separation concept. Furthermore, proposed SEUH-12T exhibits 8.5<span><math><mo>×</mo></math></span>/ 6.3<span><math><mo>×</mo></math></span>/ 5.6<span><math><mo>×</mo></math></span>/ 1.4<span><math><mo>×</mo></math></span>/ 1.2<span><math><mo>×</mo></math></span>/ 1.4<span><math><mo>×</mo></math></span>/ 1.04<span><math><mo>×</mo></math></span> times greater read stability than existing 6T-SRAM/ Quatro-10T/ We-Quatro-12T/ QCCS-12T/ STS-10T/ RHMC-12T/ RHWC-12T memory cells.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100092"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000695/pdfft?md5=b8d8b45fd53bbf7492079b861f851b8e&pid=1-s2.0-S2773064623000695-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138136196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A study of ZnO doped PDMS towards boosting of triboelectric energy harvester performance ZnO掺杂PDMS提高摩擦电能采集器性能的研究

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-12-01 Epub Date: 2023-10-07 DOI: 10.1016/j.memori.2023.100082

Hitesh Kr Sharma , Vijay Janyani , D. Boolchandani , Atul Kr Sharma

{"title":"A study of ZnO doped PDMS towards boosting of triboelectric energy harvester performance","authors":"Hitesh Kr Sharma , Vijay Janyani , D. Boolchandani , Atul Kr Sharma","doi":"10.1016/j.memori.2023.100082","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100082","url":null,"abstract":"<div><p>In this article, a study of ZnO doping in poly-dimethyl-siloxane (PDMS) polymer, which is used as one tribo layer in tribo-electric energy harvesters (TEG) is corroborated to enhance the electrical properties, open circuit voltage (V<sub>oc</sub>)and short circuit current (I<sub>SC</sub>). A parallel plate device configuration of metal-to-dielectric approach is carried out making use of copper as metal and PDMS polymer with ZnO doping as a dielectric film. The double sided copper tape of 99.99 % purity and 60 μm thickness is used to realize the top tribo layer whiledielectric PDMS polymer film with ZnO doping of 8 wt%, 13 wt%, and 18 wt% is spin coated at 1000 rpm on single side copper coated FR4 substrate to make the bottom tribo-electic layer. The mechanical force is applied in tapping mode on top layer by Universal Testing Machine (UTM). The prototype device is characterized by Agilent DSO, which revealed peak output voltage of 15 V, 20 V, 30 V, and 41 V and peak-to-peak output voltage 38 V, 50 V, 60 V, and 69 V in pure PDMS, PDMS+8 % ZnO, PDMS+13 % ZnO, and PDMS+18 % ZnO respectively. The output peak current is obtained 9 nA, 20 nA, 30 nA, and 32 nA and peak-to-peak current 31 nA, 49 nA, 51 nA, and 60 nA respectively. The performance of ZnO doped PDMS TEG has increased adequately, up to 68.44 % Of V<sub>oc</sub> and 71.87 % of I<sub>sc.</sub>with respect to pure PDMS. A scanning electron microscope (SEM) is used to confirm polymer film morphology and ZnO doping percentage in PDMS is validatedby energy dispersive X-ray spectroscopy.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100082"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Circuit simulation of floating-gate FET (FGFET) for logic application 浮栅场效应管(FGFET)电路仿真的逻辑应用

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-12-01 Epub Date: 2023-10-20 DOI: 10.1016/j.memori.2023.100090

Yunjae Kim , Hyoungsoo Kim , Jongwook Jeon , Seungjae Baik , Myounggon Kang

{"title":"Circuit simulation of floating-gate FET (FGFET) for logic application","authors":"Yunjae Kim , Hyoungsoo Kim , Jongwook Jeon , Seungjae Baik , Myounggon Kang","doi":"10.1016/j.memori.2023.100090","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100090","url":null,"abstract":"<div><p>In this study, a floating-gate field-effect transistor (FGFET) structure is proposed and verified through simulations. Current memory devices often rely on the von Neumann architecture which suffers from von Neumann bottleneck. The proposed FGFET is not vulnerable to the von Neumann bottleneck because the memory cell and process unit do not function separately. FGFET is composed with Sensor FET(SFET) and Vertical FET(VFET), which can form a memory node with connection of each part. Moreover, the advantage of FGFET is that the conventional CMOS process can be used. In this regard, the developed FGFET using the existing CMOS process shows that the circuit size, power consumption, and operation delay are significantly reduced compared to a conventional logic circuit. Furthermore, various circuit simulations comprising the proposed FGFET, such as an inverter and NAND/NOR gate, are performed, highlighting the advantages of the proposed FGFET. This study lays the foundation for using a CMOS-based memory logic integrated device and architecture for alleviating the von Neumann bottleneck.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"6 ","pages":"Article 100090"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064623000671/pdfft?md5=a8771122cbc125b8b210bfa707a1399d&pid=1-s2.0-S2773064623000671-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"92115859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance with disturbance-less program operation 一种具有背栅的新型栅极（GAAB）3D NAND闪存结构，可实现无干扰编程操作的高性能

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-01 Epub Date: 2023-08-06 DOI: 10.1016/j.memori.2023.100073

Jae-Min Sim , In-Ku Kang , Sung-In Hong , Changhan Kim , Changhyun Cho , Kyunghoon Min , Yun-Heub Song

引用次数: 0

Modeling and performance study of CZTS solar cell with novel cupric oxide (CuO) as a bilayer absorber 新型氧化铜（CuO）双层吸收器CZTS太阳能电池的建模与性能研究

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-01 Epub Date: 2023-10-05 DOI: 10.1016/j.memori.2023.100083

A. A. Md. Monzur-Ul-Akhir , Saiful Islam , Md. Touhidul Imam , Sharnali Islam , Tasnia Hossain , Mohammad Junaebur Rashid

{"title":"Modeling and performance study of CZTS solar cell with novel cupric oxide (CuO) as a bilayer absorber","authors":"A. A. Md. Monzur-Ul-Akhir , Saiful Islam , Md. Touhidul Imam , Sharnali Islam , Tasnia Hossain , Mohammad Junaebur Rashid","doi":"10.1016/j.memori.2023.100083","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100083","url":null,"abstract":"<div><p>A Kesterite material like CZTS provides the steering to the researcher with their tunable bandgap and high optical coefficient above 10<sup>4</sup> cm<sup>−1</sup> for solar cells. These features make it a suitable material for a single junction solar cell increasing the acceptance as well. In this paper, comparative numerical simulations were performed on a regular base structure of CZTS absorber layer with a CdS buffer layer, a ZnO window layer, and a transparent n-ITO conducting layer with a proposed structure where CZTS absorber layer is replaced by a CZTS and CuO bi-layer using SCAPS-1D software to optimize the efficiency. In addition to that the thickness, defect densities and doping concentrations of the absorber layers and temperature were varied to observe the responses of open-circuit voltage (<em>V</em><sub>OC</sub>), short-circuit current (<em>J</em><sub>SC</sub>), fill factor (FF) and efficiency (<em>η</em>) of the solar cell. Among the three basic researchs on lost mechanism for kesterite materials, we have focused on improving the back contact interface recombination through an absorber bi-layer combination of CZTS and CuO resulting in increased V<sub>OC</sub>, Quantum efficiency and carrier generation efficiency approximately by 50 %, 8.94 %, and 34 % respectively, elevating the efficiency of the proposed structure to 19.92 %.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100083"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50194263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide 考虑高k栅氧化物对SOI基GaN FinFET直流和模拟/RF性能的影响

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-01 Epub Date: 2023-09-12 DOI: 10.1016/j.memori.2023.100079

Vandana Singh Rajawat , Ajay Kumar , Bharat Choudhary

{"title":"Impact on DC and analog/RF performances of SOI based GaN FinFET considering high-k gate oxide","authors":"Vandana Singh Rajawat , Ajay Kumar , Bharat Choudhary","doi":"10.1016/j.memori.2023.100079","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100079","url":null,"abstract":"<div><p>This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence band energy, and subthreshold swing is reported. All these parameters are analyzed and compared with bulk GaN FinFET and Si FinFET. We achieve better ON current, faster speed, and more minor subthreshold swing, reducing the short channel effects. A shallow OFF current is obtained because of bulk conduction in the GaN channel area, which the gate can deplete. Several RF/analog metrics are also noted, including transconductance (g<sub>m</sub>), cut-off frequency (f<sub>T</sub>), transconductance frequency product (TFP), and transconductance generation factor (TGF), and comparison with Bulk GaN FinFET and Si FinFET is presented. Finally, the linearity metrics like 2nd and 3rd-order voltage intercept points, IIP3, and 1-dB compression point is extracted. Compared to the other two structures, the suggested structure exhibits advantageous DC and RF/analog performances. A comparison of different Figures of Merits (FoMs) for the suggested device with previously published literature is also given.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100079"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50193735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Toolflow for the algorithm-hardware co-design of memristive ANN accelerators 忆阻神经网络加速器算法硬件协同设计的工具流

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-01 Epub Date: 2023-06-30 DOI: 10.1016/j.memori.2023.100066

Malte Wabnitz, Tobias Gemmeke

引用次数: 0

Materials and challenges of 3D printing of emerging memory devices 新兴存储设备3D打印的材料和挑战

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-01 Epub Date: 2023-07-20 DOI: 10.1016/j.memori.2023.100067

Iulia Salaoru, Swapnodoot Ganguly, Dave Morris, Shashi Paul

引用次数: 0

Analyzing the impact of parasitics on a CMOS-Memristive crossbar neural network based on winner-take-all and Hebbian rule 基于赢者通吃和Hebbian规则的CMOS忆阻交叉神经网络寄生效应分析

Memories - Materials, Devices, Circuits and Systems Pub Date : 2023-10-01 Epub Date: 2023-10-06 DOI: 10.1016/j.memori.2023.100081

Sherin A. Thomas , Rohit Sharma , Devarshi Mrinal Das

{"title":"Analyzing the impact of parasitics on a CMOS-Memristive crossbar neural network based on winner-take-all and Hebbian rule","authors":"Sherin A. Thomas , Rohit Sharma , Devarshi Mrinal Das","doi":"10.1016/j.memori.2023.100081","DOIUrl":"https://doi.org/10.1016/j.memori.2023.100081","url":null,"abstract":"<div><p>For cognitive tasks and classifications, neuromorphic systems have shown great potential. This paper presents a novel architecture using CMOS memristive synapses where the memristors are trained using the Hebbian rule, and the winner-take-all mechanism is used for the recognition task. The proposed architecture offers a simplified approach compared to previous state-of-the-art works, making it accessible for implementing pattern recognition tasks with in-memory computation. As the size of the memristive switching devices is in the nanometer scale, designing, modeling, and optimizing the system becomes increasingly complex. This complexity leads to various signal integrity issues that arise due to parasitic components of the crossbar. A crossbar array architecture is designed using the extracted crossbar’s parasitic components obtained using the Q3D extractor. The modeled architecture provides insight into the crossbar array’s parasitic affect behavior at the schematic level for different real-time applications and how the parasitics of the crossbar will affect the fidelity and performance of the system. The proposed architecture uses a threshold-based post-synaptic neuron, which does not require any capacitor, unlike the LIF neuron, and occupies a smaller area. A neuron refractory controller is designed to make the training process efficient by keeping track of the neuron already fired and preventing it from firing in the consecutive training phase. The CMOS memristive synapse uses an average of 0.32 <span><math><mrow><mi>n</mi><mi>J</mi></mrow></math></span> energy to recognize each pattern, much less than earlier works. The proposed architecture is validated using 180 nm CMOS technology.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100081"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50194262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0