{"title":"MLTDRC: Machine learning driven faster timing design rule check convergence","authors":"Santanu Kundu","doi":"10.1016/j.memori.2023.100070","DOIUrl":null,"url":null,"abstract":"<div><p>Timing design rule check (T-DRC) convergence follows an iterative procedure like physical design closure. On a medium-complex design, the conventional flow of T-DRC convergence requires about 14 h per iteration, which includes fill insertion, sign-off accurate standard parasitic extraction format generation, sign-off static timing analysis, engineering change order (ECO) list generation in the multi-corner multi-mode scenario, fill removal, and implementation of the ECO on the pre-fill design. The T-DRC values generated from the pre-fill stage auto-place and route tool often have a miscorrelation with the sign-off values obtained from the static timing analysis tool. Due to the correlation gap, designers prefer to wait for the ECO change list to be created by the sign-off tool at the end of each iteration rather than resolve it at the pre-fill stage in the construction tool. Hence, T-DRC convergence is a lengthy process. This paper discusses an automatic T-DRC convergence methodology driven by machine learning (ML) techniques. By anticipating the transition of the input pin of a cell and the capacitance of its output pin, the suggested methodology shortens the runtime of each iteration. Additionally, it forecasts the suitable buffer to correct the T-DRC violation in the case of buffer insertion. With almost accurate prediction of T-DRC values using the ML approach, the sign-off flow can now be bypassed for a few iterations during the timing convergence phase, resulting in fewer iterations in the T-DRC sign-off flow. The violation percentage and the desired buffer name are obtained from the ML prediction result for each violation. An automatic in-house T-DRC fixer flow is developed to correct the violating elements beforehand, saving around 12 h of runtime for each iteration. Since ML prediction can never be 100% accurate, the final timing sign-off should always be done with the sign-off tool and flow to ensure zero silicon bug. With the help of ML prediction and the T-DRC fixer methodology, T-DRC convergence is possible in fewer sign-off tool iterations, resulting in a left shift of about two weeks in the timing closure cycle on the actual project execution.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"5 ","pages":"Article 100070"},"PeriodicalIF":0.0000,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Memories - Materials, Devices, Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S2773064623000476","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Timing design rule check (T-DRC) convergence follows an iterative procedure like physical design closure. On a medium-complex design, the conventional flow of T-DRC convergence requires about 14 h per iteration, which includes fill insertion, sign-off accurate standard parasitic extraction format generation, sign-off static timing analysis, engineering change order (ECO) list generation in the multi-corner multi-mode scenario, fill removal, and implementation of the ECO on the pre-fill design. The T-DRC values generated from the pre-fill stage auto-place and route tool often have a miscorrelation with the sign-off values obtained from the static timing analysis tool. Due to the correlation gap, designers prefer to wait for the ECO change list to be created by the sign-off tool at the end of each iteration rather than resolve it at the pre-fill stage in the construction tool. Hence, T-DRC convergence is a lengthy process. This paper discusses an automatic T-DRC convergence methodology driven by machine learning (ML) techniques. By anticipating the transition of the input pin of a cell and the capacitance of its output pin, the suggested methodology shortens the runtime of each iteration. Additionally, it forecasts the suitable buffer to correct the T-DRC violation in the case of buffer insertion. With almost accurate prediction of T-DRC values using the ML approach, the sign-off flow can now be bypassed for a few iterations during the timing convergence phase, resulting in fewer iterations in the T-DRC sign-off flow. The violation percentage and the desired buffer name are obtained from the ML prediction result for each violation. An automatic in-house T-DRC fixer flow is developed to correct the violating elements beforehand, saving around 12 h of runtime for each iteration. Since ML prediction can never be 100% accurate, the final timing sign-off should always be done with the sign-off tool and flow to ensure zero silicon bug. With the help of ML prediction and the T-DRC fixer methodology, T-DRC convergence is possible in fewer sign-off tool iterations, resulting in a left shift of about two weeks in the timing closure cycle on the actual project execution.