MLTDRC:机器学习驱动的更快时序设计规则检查收敛性

Santanu Kundu
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摘要

时序设计规则检查(T-DRC)收敛遵循类似物理设计闭包的迭代过程。在中等复杂的设计中,T-DRC收敛的常规流程每次迭代需要大约14小时,包括填充插入、签核精确的标准寄生提取格式生成、签核静态时序分析、多角多模场景中的工程变更单(ECO)列表生成、填充去除以及预填充设计中ECO的实现。从预填充阶段自动放置和布线工具生成的T-DRC值通常与从静态时序分析工具获得的签核值存在误相关。由于相关性差距,设计师更喜欢在每次迭代结束时等待签署工具创建ECO更改列表,而不是在构建工具的预填充阶段解决它。因此,T-DRC收敛是一个漫长的过程。本文讨论了一种由机器学习(ML)技术驱动的自动T-DRC收敛方法。通过预测单元的输入引脚和输出引脚的电容的转换,所提出的方法缩短了每次迭代的运行时间。此外,它预测了合适的缓冲区,以在插入缓冲区的情况下纠正T-DRC违规。通过使用ML方法几乎准确地预测T-DRC值,现在可以在定时收敛阶段绕过签署流进行几次迭代,从而减少T-DRC签署流的迭代次数。从每个违规的ML预测结果中获得违规百分比和期望的缓冲区名称。开发了一个自动的内部T-DRC修复程序流,以预先纠正违规元素,为每次迭代节省大约12小时的运行时间。由于ML预测永远不可能100%准确,因此应始终使用签核工具和流程进行最终的时间签核,以确保零硅错误。在ML预测和T-DRC固定器方法的帮助下,T-DRC收敛可以在更少的签核工具迭代中实现,导致实际项目执行的时间关闭周期左移约两周。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
MLTDRC: Machine learning driven faster timing design rule check convergence

Timing design rule check (T-DRC) convergence follows an iterative procedure like physical design closure. On a medium-complex design, the conventional flow of T-DRC convergence requires about 14 h per iteration, which includes fill insertion, sign-off accurate standard parasitic extraction format generation, sign-off static timing analysis, engineering change order (ECO) list generation in the multi-corner multi-mode scenario, fill removal, and implementation of the ECO on the pre-fill design. The T-DRC values generated from the pre-fill stage auto-place and route tool often have a miscorrelation with the sign-off values obtained from the static timing analysis tool. Due to the correlation gap, designers prefer to wait for the ECO change list to be created by the sign-off tool at the end of each iteration rather than resolve it at the pre-fill stage in the construction tool. Hence, T-DRC convergence is a lengthy process. This paper discusses an automatic T-DRC convergence methodology driven by machine learning (ML) techniques. By anticipating the transition of the input pin of a cell and the capacitance of its output pin, the suggested methodology shortens the runtime of each iteration. Additionally, it forecasts the suitable buffer to correct the T-DRC violation in the case of buffer insertion. With almost accurate prediction of T-DRC values using the ML approach, the sign-off flow can now be bypassed for a few iterations during the timing convergence phase, resulting in fewer iterations in the T-DRC sign-off flow. The violation percentage and the desired buffer name are obtained from the ML prediction result for each violation. An automatic in-house T-DRC fixer flow is developed to correct the violating elements beforehand, saving around 12 h of runtime for each iteration. Since ML prediction can never be 100% accurate, the final timing sign-off should always be done with the sign-off tool and flow to ensure zero silicon bug. With the help of ML prediction and the T-DRC fixer methodology, T-DRC convergence is possible in fewer sign-off tool iterations, resulting in a left shift of about two weeks in the timing closure cycle on the actual project execution.

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