IEEE open journal of circuits and systems最新文献_第8页

Research on Model Parameter Identification of Lithium Ion Battery 锂离子电池模型参数辨识研究

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.12677/ojcs.2023.122002

启煌朱

引用次数: 0

Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers PVT变化和阈值选择对RFCMOS放大器OBT和OBIST故障检测的影响

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2022.3232638

Hendrik P. Nel;Fortunato Carlos Dualibe;Tinus Stander

{"title":"Influence of PVT Variation and Threshold Selection on OBT and OBIST Fault Detection in RFCMOS Amplifiers","authors":"Hendrik P. Nel;Fortunato Carlos Dualibe;Tinus Stander","doi":"10.1109/OJCAS.2022.3232638","DOIUrl":"https://doi.org/10.1109/OJCAS.2022.3232638","url":null,"abstract":"Oscillation-based testing (OBT) and Oscillation-based built-in self-testing (OBIST) circuits enable detection of catastrophic faults in analogue and RF circuits, but both are sensitive to process, voltage and temperature (PVT) variation. This paper investigates 15 OBT and OBIST feature extraction strategies, and four approaches to threshold selection, by calculating figure-of-merit (FOM) across PVT variation. This is done using a 2.4 GHz LNA in <inline-formula> <tex-math notation=\"LaTeX\">$0.35 mu mathrm{m}$ </tex-math></inline-formula> CMOS as DUT. Of the 15 feature extraction approaches, the OBT approaches are found more effective, with some benefit gained from switched-state detection. Of the four approaches to threshold selection (nominal-ranged static thresholds, extreme-range static thresholds, temperature dynamic thresholds, and simple noise-filtered tone detection), dynamic thresholds resulted in the highest average FoM of 0.919, with the best FoM of 0.952, with a corresponding probability of test escape <inline-formula> <tex-math notation=\"LaTeX\">$Pleft(T_Eright)$ </tex-math></inline-formula> and yield loss <inline-formula> <tex-math notation=\"LaTeX\">$Pleft(Y_Lright)$ </tex-math></inline-formula> of <inline-formula> <tex-math notation=\"LaTeX\">$5 cdot 10^{-2}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation=\"LaTeX\">$1.89 cdot 10^{-2}$ </tex-math></inline-formula> respectively but requires accurate temperature measurement. Extreme static threshold selection resulted in a comparable average FoM of 0.912, but with less susceptibility to process variation and without the need for temperature measurement. Binary detection of a noise-filtered oscillating tone is found the least complex approach, with an average FoM of 0.891.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"70-84"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10002329.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An On-Chip Fully Connected Neural Network Training Hardware Accelerator Based on Brain Float Point and Sparsity Awareness 基于脑浮点数和稀疏度感知的片上全连接神经网络训练硬件加速器

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3245061

Tsung-Han Tsai;Ding-Bang Lin

{"title":"An On-Chip Fully Connected Neural Network Training Hardware Accelerator Based on Brain Float Point and Sparsity Awareness","authors":"Tsung-Han Tsai;Ding-Bang Lin","doi":"10.1109/OJCAS.2023.3245061","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3245061","url":null,"abstract":"In recent years, deep neural networks (DNNs) have brought revolutionary progress in various fields with the advent of technology. It is widely used in image pre-processing, image enhancement technology, face recognition, voice recognition, and other applications, gradually replacing traditional algorithms. It shows that the rise of neural networks has led to the reform of artificial intelligence. Since neural network algorithms are computationally intensive, they require GPUs or accelerated hardware for real-time computation. However, the high cost and high power consumption of GPUs result in low energy efficiency. It recently led to much research on accelerated digital circuit hardware design for deep neural networks. In this paper, we propose an efficient and flexible neural network training processor for fully connected layers. Our proposed training processor features low power consumption, high throughput, and high energy efficiency. It uses the sparsity of neuron activations to reduce the number of memory accesses and memory space to achieve an efficient training accelerator. The proposed processor uses a novel reconfigurable computing architecture to maintain high performance when operating Forward Propagation and Backward Propagation. The processor is implemented in Xilinx Zynq UltraSacle+MPSoC ZCU104 FPGA, with an operating frequency of 200MHz and power consumption of 6.444W, and can achieve 102.43 GOPS.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"85-98"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10051716.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Polychronous Oscillatory Cellular Neural Networks for Solving Graph Coloring Problems 求解图着色问题的多时振荡细胞神经网络

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3262204

Richelle L. Smith;Thomas H. Lee

引用次数: 1

An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS 一种超低电压单晶振荡器定时器(xo定时器)提供16 mhz和32.258 khz时钟，用于低于0.5 v的能量收集BLE无线电在28纳米CMOS

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3256368

Liwen Lin;Ka-Meng Lei;Pui-In Mak;Rui P. Martins

{"title":"An Ultra-Low-Voltage Single-Crystal Oscillator-Timer (XO-Timer) Delivering 16-MHz and 32.258-kHz Clocks for Sub-0.5-V Energy-Harvesting BLE Radios in 28-nm CMOS","authors":"Liwen Lin;Ka-Meng Lei;Pui-In Mak;Rui P. Martins","doi":"10.1109/OJCAS.2023.3256368","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3256368","url":null,"abstract":"This paper reports an ultra-low-voltage (ULV) single-crystal oscillator-timer (XO-Timer) for sub-0.5 V Bluetooth low-energy (BLE) radios that aims for self-powering by harvesting the ambient energies. Specifically, we tailor an on-chip micropower manager <inline-formula> <tex-math notation=\"LaTeX\">$(mu $ </tex-math></inline-formula>PM) to customize the voltage and current budgets for each sub-function of the XO-Timer. Such <inline-formula> <tex-math notation=\"LaTeX\">$mu $ </tex-math></inline-formula>PM shows a high power efficiency by introducing a 3-stage cascaded structure and a single voltage-regulation loop; they together uphold the performance of the XO-Timer amid supply-voltage and temperature variations. The core amplifier of the XO-Timer is ULV-enabled, and is reconfigurable (i.e., 1-stage and 3-stage gm) to balance between the power budget and performance under the high-performance mode (HPM) and low-power mode (LPM). Fabricated in 28-nm CMOS, the XO-Timer in HPM generates a 16-MHz clock with a power of <inline-formula> <tex-math notation=\"LaTeX\">$24.3 ~mu text{W}$ </tex-math></inline-formula>, and a phase noise of −133.8 dBc/Hz at 1-kHz offset, resulting in a Figure-of-Merit (FoM1) of −236 dBc/Hz. In the LPM, the XO-Timer delivers a 32.258-kHz clock while consuming <inline-formula> <tex-math notation=\"LaTeX\">$11.4 ~mu text{W}$ </tex-math></inline-formula>. The sleep-timer FoM2 is <inline-formula> <tex-math notation=\"LaTeX\">$14.8 ~mu text{W}$ </tex-math></inline-formula> and the Allan deviation is 35.1 ppb, achieving the lowest supply voltage (0.25 V) not only for a dual-mode XO-Timer but also for a MHz-range XO.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"126-138"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10068768.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Deep Reinforcement Learning on FPGA for Self-Healing Cryogenic Power Amplifier Control 基于FPGA的深度强化学习低温功率放大器自愈控制

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3282929

Jiachen Xu;Yuyi Shen;Jinho Yi;Ethan Chen;Vanessa Chen

{"title":"Deep Reinforcement Learning on FPGA for Self-Healing Cryogenic Power Amplifier Control","authors":"Jiachen Xu;Yuyi Shen;Jinho Yi;Ethan Chen;Vanessa Chen","doi":"10.1109/OJCAS.2023.3282929","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3282929","url":null,"abstract":"Wireless sensing and communication for space exploration in areas inaccessible to human often suffer from severe performance degradation due to the cryogenic effects on the transmitters’ circuits. To survive extreme temperatures, programmable radio frequency (RF) power amplifiers (PA) can be built into the transmitter, and intelligent PA controllers need to be integrated into the system to interact with the environment and restore the PA’s functionalities. This problem can be modeled as the controller acts (control the PA) in an environment to maximize the reward (signal quality), and it is most suitable to use reinforcement learning as a solution. This paper presents a cryogenic and energy-efficient reinforcement learning (RL) module on Field Programmable Gate Arrays (FPGA) that can directly program the PA. By characterizing a self-healing PA in a liquid nitrogen environment, we generated an RF signal data set and built an interactive RL environment to model the PA’s behaviors across its configurations and cryogenic temperatures down to −197°C. We developed a deep RL model with a high generalization capability introduced by the neural networks to control the PA and restore its performance. The RL model with fixed-point training and inference is implemented on FPGA to survive the cryogenic conditions and carry out fast and low-power training and inference for PA control. All functionalities of the programmed FPGA operate correctly in the cryogenic testing environment.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"176-187"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10143969.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Reversible Gates: A Paradigm Shift in Computing 可逆门:计算中的范式转变

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3305557

Syed Farah Naz;Ambika Prasad Shah

{"title":"Reversible Gates: A Paradigm Shift in Computing","authors":"Syed Farah Naz;Ambika Prasad Shah","doi":"10.1109/OJCAS.2023.3305557","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3305557","url":null,"abstract":"The reversible gate has been one of the emerging research areas that ensure a continual process of innovation trends that explore and utilizes the resources. This review paper provides a comprehensive overview of reversible gates, including their fundamental principles, design methodologies, and various applications. It also analyzes the reversible gates, comparing them based on metrics such as Quantum Cost, Complexity, and other performance evaluation measures. The analysis of several reversible gates is presented in this paper and provides a comprehensive overview of reversible gates, encompassing their fundamental principles, design methodologies, and diverse applications. Reversible logic circuits allow for the production of both unique outputs and distinct input combinations. The majority of the findings about the reversible gates from previous research papers are discussed and contrasted. All the reversible gates that have been proposed till now are presented in tabular form and the parameters are discussed to help the researchers to find every detail related to the reversible gates. To highlight our understanding, we have ended most of the sections with questions. The inclusion of questions is likely intended to stimulate further discussion and promote a deeper understanding of the material presented in this paper. These questions can serve as prompts for readers to reflect on the content and potentially explore related research directions or areas of improvement.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"241-257"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10218349.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49910075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting 一个简短的教程混合信号的方法来打击电子假冒

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3253144

Troy Bryant;Yingjie Chen;David Selasi Koblah;Domenic Forte;Nima Maghari

{"title":"A Brief Tutorial on Mixed Signal Approaches to Combat Electronic Counterfeiting","authors":"Troy Bryant;Yingjie Chen;David Selasi Koblah;Domenic Forte;Nima Maghari","doi":"10.1109/OJCAS.2023.3253144","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3253144","url":null,"abstract":"As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal approaches to combat electronic counterfeiting. An LDO-based odometer capable of accurately classifying ICs as new or aged is presented as a promising method for detecting counterfeit and recycled ICs. Additionally, this tutorial discusses the use of physical unclonable functions (PUFs) as primitives for generating cryptographic keys for digital signatures, encryption, or authentication. The design process of all PUFs is introduced and the key characteristics and evaluation metrics of state-of-the-art PUFs are defined. Finally, to promote digital IP protection, several methods for camouflaged digital gates are presented and analyzed. The threshold voltage defined (TVD) logic families discussed are capable of implementing any N-to-1 logic function and are highly resilient to reverse engineering attacks.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"99-114"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10064465.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49909919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Slimmer CNNs Through Feature Approximation and Kernel Size Reduction 通过特征逼近和核尺寸缩减使cnn更苗条

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3292109

Dara Nagaraju;Nitin Chandrachoodan

{"title":"Slimmer CNNs Through Feature Approximation and Kernel Size Reduction","authors":"Dara Nagaraju;Nitin Chandrachoodan","doi":"10.1109/OJCAS.2023.3292109","DOIUrl":"https://doi.org/10.1109/OJCAS.2023.3292109","url":null,"abstract":"Convolutional Neural Networks (CNNs) have been shown to achieve state of the art results on several image processing tasks such as classification, localization, and segmentation. Convolutional and fully connected layers form the building blocks of these networks. The convolution layers are responsible for the majority of the computations even though they have fewer parameters. As inference is used much more than training (which happens only once), it is important to reduce the computations of the network for this phase. This work presents a systematic procedure to trim CNNs by identifying the least important features in the convolution layers and replacing them either with approximations or kernels of reduced size. We also propose an algorithm to integrate the lower kernel approximation technique for a given accuracy budget. We show that using the linear approximation method can achieve a 15% – 80% savings with a median of 52% reduction while the lower kernel method can achieve 33% – 95% reduction with a median of 65% in the required number of computations with only a marginal 1% loss in accuracy across several benchmark datasets. We have also demonstrated the proposed methods on VGG-16 architecture for various datasets. On VGG-16 we have achieved 4.2% - 45% savings in MAC computations (with a median of 18.5%) with only a marginal 0.5% loss in accuracy. We also show how an existing hardware accelerator for DNNs (DianNao) can be modified with low added complexity to take advantage of the kernel approximations, and estimate the speedups that can be obtained in such a way on custom embedded hardware.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":"4 ","pages":"188-202"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8784029/10019301/10173478.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49919366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Phase Interpolator-Based Clock and Data Recovery With Jitter Optimization 基于相位插值器的时钟和数据恢复与抖动优化

IEEE open journal of circuits and systems Pub Date : 2023-01-01 DOI: 10.1109/OJCAS.2023.3295649

George Souliotis;Andreas Tsimpos;Spyridon Vlassis

引用次数: 1