2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)最新文献

{"title":"Low-temperature silver sintering by colloidal approach","authors":"Maxime Bronchy, J. Souriau, J. Heintz, C. Feautrier, D. Henry, É. Duguet, L. Mendizabal, G. Simon, M. Tréguer-Delapierre","doi":"10.1109/ESTC48849.2020.9229830","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229830","url":null,"abstract":"The interest of silver nanostructures has surged in recent years as they are becoming promising materials in a growing number of applications. In particular, they have received intense attention for their use as lead-free die attach materials, photoactive devices engineering or more broadly electronic packaging. One of the challenges is the elaboration of conductive and printable patterns by Low-Temperature and Pressureless Sintering Techniques (LTPST) to achieve electric circuits on heat-sensitive substrates such as paper, plastic, polymeric substrates. Here, we present a facile method for synthesizing conductive patterns at low temperature based on the formation of self-assembled Ag nanocubes on Active Metal Brazing (AMB) substrates. The elaboration of 3-D arrays with nanogap of 2-3 nm between the cubic building units allows to get dense and compact packed nanoparticle solids which sinter at lower temperature than conventional commercial silver pastes. The impact of the capping agent and the size of the building units on the sintering properties were investigated and discussed.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"32 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84833441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of Polysilicon Microstructures to Estimate Local Temperature on CMOS Chips","authors":"A. Roy, L. Marchetti, M. Azadmehr, P. Häfliger, B. Q. Ta, K. Aasmundtveit","doi":"10.1109/ESTC48849.2020.9229851","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229851","url":null,"abstract":"The measurement of local temperature on application specific integrated circuits (ASICs) can be used to determine the reliability of electronics implemented on the chip. For this reason, we propose a simple method to monitor the temperature on CMOS by using polysilicon microstructures realized in AMS 350 nm technology. The surrounding temperature on a CMOS chip was extracted from four-probe resistance measurement of two polysilicon microstructures fabricated during the IC manufacturing process. Electrical characterization of these microstructures was performed within 25 to 400 °C for using them as on-chip temperature sensors. The sensors were tested with in-built CMOS microheaters as heat source. Results show that an IC temperature ranging from room-temperature to 200 °C can be estimated with a deviation below 2 °C between the two sensors, while the deviation increases with higher temperature. Overall, the proposed method is simple and requires minimal measurement setup to monitor the temperature on ICs.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"141 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77287639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of Surface Finish, Solder Volume and Solder Composition on the Grain Structure of SnAgCu Solder Joints","authors":"P. Tegehall","doi":"10.1109/ESTC48849.2020.9229774","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229774","url":null,"abstract":"Lead-free solder joints based on SnAgCu solders often consist of one single tin grain. Since tin is highly anisotropic, the grain structure in SAC solder joints and the orientation of the tin grain in single-grained solder joints may have a large impact on the fatigue life of the solder joints when exposed to thermomechanical stress.The scope of this study was to evaluate how the grain structure in SAC solder joints to various BGA components is impacted by surface finishes on soldered surfaces, and the volume and composition of the solder. The grain structure was analysed by cross-sectioning of the solder joints and inspected using optical microscopy with cross-polarised light. In addition, some samples were analysed using electron backscatter diffraction in order to determine the orientation of the grains.Four grain structures were observed in the solder joints: single grained, cyclic twin, interlaced twin or mixed cyclic and interlaced twin structure. The surface finish had the largest impact on the grain structure. Solder joints formed between nickel and copper solder finishes had in most cases a high fraction of solder joints with mixed cyclic and interlaced twin grain structure whereas solder joints formed between two nickel finishes had a high fraction of single-grained solder joints.The results from this study indicate that the morphology of the intermetallic layers formed on soldered surfaces is the main factor determining the degree of undercooling during solidification.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"8 1","pages":"1-16"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87303003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Temperature Solid State Bonding of Cu-In Fine-Pitch Interconnects","authors":"Steffen Bickel, I. Panchenko, Wataru Tachikawa, M. Wolf","doi":"10.1109/ESTC48849.2020.9229826","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229826","url":null,"abstract":"Cu-In fine pitch interconnects are a viable approach for low temperature bonding technologies in 2.5 D and 3D integration. The unique metallurgical phenomena regarding the phase formation and growth of intermetallic compounds (IMCs) in the Cu-In system affect both processing conditions and the resulting interconnection properties. In this work, we investigate the formation Cu-In joints below 150 °C, i.e. in the solid state, under ambient conditions. Dies with Cu interconnects and In caps (25 µm diameter, 55 µm pitch) were bonded in a flip-chip process at moderate pressures and subsequently investigated by means of mechanical testing, cross-sectioning and microstructural analysis. In particular, we reveal the presence of stable interconnects exhibiting a ductile bonding zone. The resulting die shear strengths are in the range of 15-20 MPa.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"105 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91216576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process development and characterization of 3D multi-die stacking","authors":"C. Gerets, J. Derakhshandeh, P. Bex, M. Lofrano, V. Cherman, F. Fodor, I. De Wolf, K. Rebibis, G. Beyer, Andy Miller, E. Beyne","doi":"10.1109/ESTC48849.2020.9229814","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229814","url":null,"abstract":"In this paper the stacking process development and the characterizations of multi-die stacks N=16, which contain 15 thinned top dies on a bottom die, are described. A comparison study between sequential and vertical collective bonding, to see the impact on their characteristics is examined in detail. Also, an in-situ temperature measurement during stacking is performed and a simulation is done to find the proper thermo compression bonding (TCB) profile to stack a large number of dies with good soldering connection also on the bottom die. Multi-die stacks with high alignment accuracy and good electrical yield (e-yield) are made and characterized by cross-section SEM, SAM and X-RAY analysis.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"101 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74944163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Plasma Dicing of Wafers for Reduced Total Cost of Ownership and Increased Quality","authors":"J. Weber, Shogo Okita","doi":"10.1109/ESTC48849.2020.9229763","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229763","url":null,"abstract":"It could be argued that the defining feature of the Electronics Industry is the ability to miniaturize. Every person with a passing interest in electronics has heard of Moore’s Law: the processing power of affordable CPUs - or the number of transistors on a chip - will roughly double every two years. It is credit to both Gordon Moore’s foresight, and the technical and engineering teams around the world who continue to innovate, that the ‘Law’ is still even being discussed today. Part of the reason for chip size reduction lies in the shrinking of technology nodes (process geometries). Currently the smallest node that is being manufactured in mass volume is 7nm, and even smaller sizes are under development in the industry. The increase in processing power and speed and the miniaturization and integration of electronic functions that continue to result from such technological advances lie at the heart of the pervasiveness of electronics in our everyday lives: the smart phones that we rely on; the uptake of artificial intelligence in smart homes and cities; driverless vehicles; remote medical home diagnostics - there is not one aspect of life that electronic products and systems have not penetrated. But for this to continue, it is not only in the area of photolithographic processing that technology needs to keep innovating. Once a wafer has been created it must be singulated into individual dies, and as dies are becoming smaller and thinner, many products are facing difficulties caused by the singulation or dicing process. New challenges include: increasing material loss due to the width of the dicing street; mechanical damage such as chipping; and increasing processing time.Panasonic has developed a plasma dicing process which addresses these issues and in certain circumstances can replace mechanical dicing. Advantages of plasma dicing are:i.Damage-free / Chipping-free processii.Increased chip yield per waferiii.Water-free processiv.Flexible chip shapev.Fast etching speedvi.Total Dicing Process FlowThe throughput of a plasma chamber depends mainly on wafer thickness and wafer material, and is quite independent from wafer size or chip size. By using plasma dicing, the throughput can be more than 4 or 5 wafers per hour. Such throughput cannot be achieved by any line-by-line dicing method when small chips are required. Significant cost savings can be expected.The combination of higher throughput and increased chip yield per wafer lead to an overall reduced total cost of ownership, and the damage-free / chipping-free nature of plasma dicing leads to an increase of chip-strength and overall quality.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"130 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79836345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Grain Structure Analysis of Cu/SiO2 Hybrid Bond Interconnects after Reliability Testing","authors":"I. Panchenko, L. Wambera, Maik Mueller, C. Rudolph, A. Hanisch, I. Bartusseck, M. Wolf","doi":"10.1109/ESTC48849.2020.9229743","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229743","url":null,"abstract":"The focus of this study is a grain structure analysis of hybrid Cu/SiO2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding also known as direct bond interconnect is a very promising technology for fine pitch bonding without solder capped microbumps. The elimination of solder enables smaller bonding pitches and smaller interconnect sizes. The main challenge of the hybrid bonding technology is the preparation of a clean Cu/SiO2 surface with a required Cu dishing. The development of the Cu grain structure after hybrid bonding and after reliability testing was investigated in detail in this study. The wafer-to-wafer stack with Cu interconnects (diameter 4 μm and pitch 18 μm) enclosed by SiO2 was prepared. This wafer stack was diced into small pieces after successful bonding for further reliability testing. Two types of tests were carried out according to JEDEC standards: temperature shock test at −40°C / +125°C with up to 1000 cycles and isothermal storage at 150°C, 300°C, and 400°C. The resulting microstructure was characterized by scanning electron microscopy (SEM) and electron backscatter diffraction (EBSD). The results show that Cu/Cu interconnects have a {111} texture parallel to the bonding interface that barely changes with reliability testing. EBSD indicates the intergrowth between the Cu grains after the isothermal storage. Significant grain coarsening was found for the isothermal storage at 400 °C in comparison to the state after bonding. The details of the bonding interface (defects and grain boundaries) are presented as well and discussed with regard to recent publications.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"113 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75763969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A numerical study of heat transfer in PCM composites for the integration of batteries and power electronics","authors":"Li Zhang, S. Liang, Zhaoxia Zhou, Xiaoxiao Han, Changqing Liu","doi":"10.1109/ESTC48849.2020.9229794","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229794","url":null,"abstract":"The heterogeneous integration of lithium-ion batteries and power electronics in electric vehicles (EVs) application receives great attention due to its advantages of enhanced reliability, high flexibility and multifunctionality. However, the construction of the integration of batteries with power electronics presents a challenge in terms of the thermal management due to the temperature sensitivity of batteries. The heat generated by power electronics degrades the performance and life of batteries. This paper presents a numerical analysis of the heat transfer characteristics in phase change materials (PCM) composites within a system combining a battery cell with power electronics to investigate the effect of PCM composites on the heat transfer behaviour. The thermal analysis of PCM composites was conducted using a finite element model and compared with the results in literature. The findings indicate that PCM composites effectively delayed the temperature increase near the battery cell side and the power electronics side due to the large heat storage capacity of PCM. Moreover, the temperature increased more slowly when the porosity of PCM composites was higher. This study further demonstrates the effectiveness of PCM composites for thermal management applications of the integration of lithium-ion batteries and power electronics.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"24 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75664548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer bonding process for zero level vacuum packaging of MEMS","authors":"G. Sordo, C. Collini, S. Moe, E. Poppe, D. N. Wright","doi":"10.1109/ESTC48849.2020.9229871","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229871","url":null,"abstract":"It is well known that the packaging of electronic devices is of paramount importance, none more so than in MEMS were fragile mechanical elements are realized. Among the different approaches, wafer to wafer bonding guarantees the advantages of the wafer scaling and provides protection of the devices during the final phase of fabrication. Direct bonding, also known as fusion bonding, is seldom implemented in MEMS fabrication due to the high surface quality required, the high temperature involved and the compulsory wet activation process. In this paper a direct bonding process for MEMS inertial sensor without the need of any wet activation step is presented.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"78 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80238180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Framework to Assess the Security of Advanced Integrated Circuit (IC) Packaging","authors":"Chengjie Xi, Nathan Jessurun, N. Asadizanjani","doi":"10.1109/ESTC48849.2020.9229713","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229713","url":null,"abstract":"Packaging reliability has been discussed widely in both industry and academia. However, packaging security assessment is barely addressed in such communities. Adversarial changes in packaging parameters by a malicious manufacturer can result in undetected features, which can cause chip failure. Due to globalization and complexity of the microelectronics supply chain, such alterations can be easily implemented. A dishonest manufacturer can intentionally exploit packaging principles thus creating vulnerabilities in the chip nearly undetectable by the regular inspection process. This can cause severe problems in both short term and long term uses of the chip. Both cases are directly related to changes in packaging materials, namely the epoxy modeling compound, substrate material, and connection material. These hostile changes are even more difficult to detect post-manufacturing, as is the case for the end-users performing their own analysis on such chips. This is not only because the existing material characterization methods are destructive and time-consuming, but there are numerous unpredictable ways to maliciously change packaging property. In this paper, we will first study and analyze such vulnerabilities in advanced integrated circuit (IC) packaging and introduce the first ever taxonomy of vulnerabilities to the community to the best of our knowledge. To address the discussed shortfalls in packaging security assessment, this paper will also outline the requirements for new detection techniques necessary to address the packaging security before installation. These methods are especially useful in critical applications such as space, military, hospitals, power plants, etc.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"146 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79954992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}