Grain Structure Analysis of Cu/SiO2 Hybrid Bond Interconnects after Reliability Testing

Abstract

The focus of this study is a grain structure analysis of hybrid Cu/SiO2 wafer-to-wafer bonding interconnects after reliability testing. Hybrid bonding also known as direct bond interconnect is a very promising technology for fine pitch bonding without solder capped microbumps. The elimination of solder enables smaller bonding pitches and smaller interconnect sizes. The main challenge of the hybrid bonding technology is the preparation of a clean Cu/SiO2 surface with a required Cu dishing. The development of the Cu grain structure after hybrid bonding and after reliability testing was investigated in detail in this study. The wafer-to-wafer stack with Cu interconnects (diameter 4 μm and pitch 18 μm) enclosed by SiO2 was prepared. This wafer stack was diced into small pieces after successful bonding for further reliability testing. Two types of tests were carried out according to JEDEC standards: temperature shock test at −40°C / +125°C with up to 1000 cycles and isothermal storage at 150°C, 300°C, and 400°C. The resulting microstructure was characterized by scanning electron microscopy (SEM) and electron backscatter diffraction (EBSD). The results show that Cu/Cu interconnects have a {111} texture parallel to the bonding interface that barely changes with reliability testing. EBSD indicates the intergrowth between the Cu grains after the isothermal storage. Significant grain coarsening was found for the isothermal storage at 400 °C in comparison to the state after bonding. The details of the bonding interface (defects and grain boundaries) are presented as well and discussed with regard to recent publications.