2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)最新文献

{"title":"MOCVD Al(Ga)N Insulator for Alternative Silicon-On-Insulator Structure","authors":"G. Ross, Ville Luntinen, M. Broas, S. Suihkonen, T. Tuomi, A. Lankinen, A. Danilewsky, M. Tilli, M. Paulasto-Kröckel","doi":"10.1109/ESTC48849.2020.9229836","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229836","url":null,"abstract":"Due to the functional limitations of SiO2 for SOI applications, alternative dielectric materials have been investigated. Alternative SOI materials in this work include, AlN and AlGaN. The dielectrics were deposited using MOCVD, and with the aid of PECVD deposited SiO2, and the SiO2 was directly bonded to a handle Si wafer. Tensile tests were performed on the samples to examine the fracture behavior and maximum tensile stresses, with results being comparable to a traditional SOI. Characterization was undertaken using TEM to understand the microstructural and interfacial properties of alternative SOI. High crystal quality Al(Ga)N was achieved on a Si(111) substrate that generally contained well defined chemical interfaces. Finally, synchrotron X-ray diffraction topography was used to understand the topographical strain profile of the device and handle wafers. Topography results showed different strain network properties between the device and handle wafer. This work has demonstrated preliminary feasibility of using alternative dielectrics for SOI applications.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"66 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84076530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Post-Binary Robotics: Using Memristors With Ternary States for Robotics Control","authors":"Steven Bos, Julian Breivold Nilsen, H. Gundersen","doi":"10.1109/ESTC48849.2020.9229820","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229820","url":null,"abstract":"This paper presents a method to read and write ternary (three-valued) signals on memristors to control a robotic actuator in real-time. The paper is a continuation of earlier work by [1] and implements a ternary memory controller for memristors in hardware. This post-binary approach with nonvolatile memory is used to program a memristor as a \"trit\". The paper contributes to the state-of-the-art in memristor controlled robotics by reporting an entropy gain of log2(3)= 58% information at (20 versus 14)= 43% more component cost compared to binary. This advantage (eg. less wire complexity) increases when multi-trit architectures are considered.This article demonstrates both an LTspice simulation of the circuit and implementation with source code. The memristor programmer circuit writes a state to the memristor using a pattern of 100us pulses at 3 different amplitudes. The memristor read circuit sends 500 nA pulses and converts these using two reference resistors to three logic levels using an op amp window comparator. An Arduino Mega microcontroller ADC pin converts the analog output to a digital trit. Strenuous effort was made for predictable and replicable applied memristor research in pursuit of a post-binary robotics era. The multiple-valued circuit has safety features to prevent harm to the memristance state, standardized forming of new memristors and programming flexibility by sending patterns of different pulse amounts, pulse width and pulse amplitudes.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84245249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly Integrated Assembly Processes Solutions for Double-Sided-SiP Package","authors":"B. Ma, D. Ho, Yu-Po Wang, F. Yen, Shawn Guo, Ryan Chiu","doi":"10.1109/ESTC48849.2020.9229680","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229680","url":null,"abstract":"5G era is coming, mobile devices with high performance and high duration ability have been common requirement in recent years. By shrinking PCB size to enlarge battery size seems like a simple way. However, there will be more and more components integrated into a smartphone devices so IC packaging would require the feature of small form factor with integrating inductors, capacitors and resistors into a single module. Today, an emerging 3D packaging solution aka Double-Sided-SiP could offer higher integration ability as well as addressing space limitation.In this paper, a double side molding process will be used forming the Double-Sided-SiP structure which integrates lots passive components on the top side of Double-Sided-SiP are assembled by SMT, and SoC die on the bottom side is surrounded by BGA ball and epoxy molding compound. This kind of packaging platforms are able to shrink overall package size around 35%. However, to provide sufficient related current and voltage usually use bulky passives for this kind of applications. It means that top mold must be tall enough to accommodate the bulky passives. With overall package height constraints, an extremely unbalanced mold ratio between top mold and bottom mold is expected to cause worse warpage performance. Another major challenge is to make BGA ball solder protrusion for sufficient stand of height proceeding to SMT assembly process.In this study theme, warpage simulation for strip form and package unit form will be implemented for epoxy molding compound selection. Afterward, using DOE (Design of Experiment) study to verify warpage performance post molding will be implemented. Another DOE study to find out proper laser ablation process parameter will be performed to reach designate BGA ball solder protrusion as well. In addition, a series typical reliability testing, including TCT(Temperature Cycle Test), HTST(High Temperature Storage Test), un-bias HAST are eventually carried out as verification of the Double-Sided-SiP structure.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"58 33 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76046514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal and Electro-Thermal Analysis of DC-DC convertor for 3 wheeler electric vehicle","authors":"Ritwik Alok Pattnayak, Bhushan Manapadam Baskar","doi":"10.1109/ESTC48849.2020.9229677","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229677","url":null,"abstract":"The power electronics involved in 3-wheeler electric vehicles are exposed to rough and challenging thermal environments which can have a damaging effect on the thermal reliability of the electric components on the electric vehicles. One such critical power electronic section of electric vehicles is DC-DC convertor which converts a source of direct current from one voltage level to another voltage level. DC-DC convertor is used to interface the elements in the electric powertrain by boosting or chopping the voltage levels. Due to automotive constraints, the power convertor structure has to be reliable, lightweight, small volume, with high efficiency, low electromagnetic interference and low current/voltage ripple. The difference between DC-DC convertor for a 4-wheeler and 3- wheeler is that the previous one is isolated and has a bigger size and higher thermal loads whereas the latter is non isolated with lower thermal loads. The challenge for 3-wheeler DC-DC is that the heat load has to be contained by natural convection and conduction mode only. Moreover, for the DC-DC to be thermally reliable the internal air temperature has to be maintained below 100 °C. The product consists of a top and bottom enclosure with heat sink and fins, PCB, surface mount electronic components on PCB, potting material, thermal interface material between PCB and bottom heat sink. The PCB is a multilayer CU-FR4 board, no forced air flow is allowed at the mounting location. First the placement of components was optimized with electro thermal analysis of the PCB board to see areas in the copper traces with high current density and high joule heating. By doing an electro thermal analysis with the help of FloThermXT we arrived at the required trace width and design and then the optimized placement of components was done in order to take care of joule heating aspect. Further after the complete placement of components were done the entire steady state thermal analysis of DC-DC was done first without potting material and then with potting material so as to the see the effect of potting material on the internal air temperature inside the product. The difference between simulation results and measurement is a cumulative average of 10.5 %. The usage of potting material helps in approximate of 5% reduction of temperature. A well-established correlation between experimental and numerical method for thermal analysis of DC-DC for 3 -wheeler electric vehicle has been achieved.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"107 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83198724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low equivalent series resistance (ESR) silicon-based on-chip supercapacitors","authors":"K. Du, Chengjun Yu, P. Øhlckers, Xuyuan Chen","doi":"10.1109/ESTC48849.2020.9229873","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229873","url":null,"abstract":"In this paper, we report the fabrication and optimization of current collectors on the supercapacitors based on a black silicon substrate with highly-dense carbon nanotube layers grown by atmospheric pressure chemical vapor deposition (APCVD) method for low equivalent series resistance (ESR). The as-grown CNTs displayed an excellent capacitive behavior with the corresponding specific capacitance of 126.7 mF/cm2 in the organic electrolyte at the scan rate of 10 mV/s. In order to reduce the ESR, we presented a feasible fabrication method to form a top Au current collector on the CNTs layer by DC sputtering technology. After coated with the Au layer, the ESR of the coin-cell type supercapacitor is reduced by 31% from 0.19 Ω/cm2 to 0.13 Ω/cm2. These results show that the top Au current collector could improve the performances for on-chip supercapacitors. We also expect this method could bring a potential breakthrough in the mass production of on-chip supercapacitors.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"10 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75888782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of UBM oxidation through air exposure and heating and effectiveness of wet and plasma cleaning on solder joint formation during TCB","authors":"S. Hossein Mirdamadi, J. Derakhshandeh, T. Cochet, E. Beyne, G. Beyer, Andy Miller","doi":"10.1109/ESTC48849.2020.9229662","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229662","url":null,"abstract":"In 3D stacking chips, interconnections play an important role and selection of right materials is very significant. In this paper, a systematic study is done to characterize metal oxide growth rate with time and temperature for three most used UBM (under bump metallization) materials i.e. copper, cobalt, and nickel for the interconnections. Furthermore, effectiveness of two cleaning techniques such as wet cleaning and plasma cleaning before TCB (thermo compression bonding) process is investigated. As the metal oxidation, depending on air exposure through time, needs a quick and accurate evaluation, SE (spectroscopic ellipsometry) is employed to measure optical phase quantity (Delta) and thickness. To monitor grain size evolution and measure roughness of the sample surface, AFM (Atomic Force Microscopy) is used. Moreover, wettability of the materials surface, as a key factor in bonding, is measured by Contact Angle tool. As copper is considered a main material for UBM, TOF-SIMS (time of flight second ion mass spectroscopy) as well as XRD (X-ray diffraction) techniques were selected to investigate oxidation concentration along depth profile and oxide phase of the surfaces for the samples respectively and cross section of the oxide layer is observed through SEM.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"44 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91254249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Densely packed hollow structured carbon with graphene-like shells on carbon cloth for high power supercapacitors","authors":"P. Lu, Xuyuan Chen","doi":"10.1109/ESTC48849.2020.9229682","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229682","url":null,"abstract":"Supercapacitors are effective energy storage devices for electronics, with a prominent characteristics of high power density. Electrode design is an essential topic in the research of supercapacitors. In this study, we demonstrate a new type of supercapacitor electrodes and their fast charging/discharging application potential. Specifically, (1) Co-based compound nanowire arrays were first grown onto the carbon cloth by a facile hydrothermal route. (2) A chemical vapor deposition (CVD) process was subsequently performed, involving the in-situ thermal transformation of Co-based compound nanowire arrays to densely packed metallic sub-micron Co particles, and the following metallic cobalt catalyzed growth of nano-carbons onto the Co particles. (3) An acid etching process was finally carried out to remove the Co particles, leading to the formation of hollow structured carbon electrode materials on carbon cloth substrate. High magnification scanning electron microscopy (SEM) and element mapping technologies revealed the clear graphene-like carbon shells, and the intriguing hollow structure. Benefiting from the porous framework of carbon cloth for favorable accommodation of electrode materials, and the new type CVD produced hollow structured carbon particles with graphene-like shells for superior electronic and ionic conductivity, the electrode performance in three-electrode measurement indicates an successful electrode design.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"76 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72938308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal evaluation of metalized ceramic substrates for use in next-generation power modules toward international standardization","authors":"Naoki Wakasugi, Chuantong Chen, K. Hirao, S. Nagao, K. Suganuma","doi":"10.1109/ESTC48849.2020.9229827","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229827","url":null,"abstract":"Wide bandgap (WBG) semiconductors such as SiC and GaN have opened their market as the next generation of high power modules. As advanced electronic power modules must deal with increasing power density, power modules with an insulating ceramic substrate are subjected to extremely high temperature due to high current and voltage. Currently, the junction temperature of Si power devices is kept low enough, around 150 ℃, to maintain the module durability. Nevertheless, the temperature will be soon beyond 200 ℃ for WBG devices. Thus thermal dissipation performance has one of the key technologies in designing modules. Directly bonded copper (DBC) or aluminum (DBA) substrates have been widely used as two of the typical ceramic insulating substrates for high power modules. If the extensive heat from a junction is kept inside a module, the module will be easily damage due to the increasing temperature resulting in severe thermal stress inside. Designing a proper module structure requires not only each material property but also complex component shape/structure/layout including each interface heat transfer. An accurate measurement method of precise thermal properties for such a complex metallized ceramic substrates is currently still missing. To meet the urgent requests for the next generation of high power modules, a new and simple measurement method of the thermal properties has been proposed for complex metallized ceramic substrates. First we have designed a micro heater SiC chip as an accurate and controllable heat source instead of a SiC active die. The heater chip was die-attached on metallized ceramic substrate mimicking real module packaging structure. The thermal resistance of the metallized ceramic substrate was evaluated. Due to the high power of the chip, i.e. 1 kW/cm2, the obtained thermal resistance has an excellent accuracy within a few percent error, when adequate cooling system is used. The thermal resistance includes those of die-attach material and thermal interface materials (TIM). The developed method thus enables precise comparison in thermal properties of high power modules, which was proposed as an ISO standard.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"6 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87431869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PSpice Model for a Current Sensor Based on Spin-Valve Magnetoresistive Microstructure","authors":"Elena-Mirela Stetco, O. Pop, M. Gabor, A. Grama, D. Pitica","doi":"10.1109/ESTC48849.2020.9229833","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229833","url":null,"abstract":"In this work a PSpice model for a spin-valve magnetoresistance microstructure current sensor was described and validated. Starting from the experimental characteristics of the sensor, the model was implemented using LookUp-Table method, which is a table-based approach to the empirical modeling. To obtain a PSpice model with a behavior closer to that of the real sensor, an improvement is made by introduction of several points on the structure characteristic, and then, using the same method based on LookUp-Table, the model was tested again. In order to achieve additional points, the equation of the characteristic was extracted in MATLAB, by interpolating the measurement points obtained by laboratory measurements with a higher order polynomial. Once the model is validated, it can be used to model other types of structures and to simulate electronic circuits that are composed of magnetic current sensors of this type.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"39 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90514815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Peristaltic Pump with Continuous Flow and Programmable Flow Pulsation","authors":"Sebastian Pech, René Richter, J. Lienig","doi":"10.1109/ESTC48849.2020.9229731","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229731","url":null,"abstract":"In future, sensors with flexible electronics will be deployed more often in biomedical applications for the acquisition of biological signals in the human body. To ensure biocompatibility, these sensors are often encapsulated by polymers. For research and testing of new encapsulation materials and their biocompatibility evaluation, new test procedures will be necessary, which reflect the flow conditions of the physiological environment. This paper presents a new peristaltic pump which stimulates the tube by a circulating eccentric oscillation. The pump characteristics differ significantly from conventional roller pumps and combine continuous flow and programmable flow pulsation. In continuous mode the non-occlusive pump can reduce the flow pulsation by about 85% in comparison to a conventional roller pump. Programmable flow pulsation is achieved by controlling the oscillation amplitude. This control characteristic enables the generation of defined volume flow pulses. Pulse shapes of a second generation vessel in the human arterial network can be generated in experimentally, for instance. These pulse shapes are required for in vitro investigations of biocompatible encapsulations under physiological flow conditions.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"23 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81987454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}