2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)最新文献

{"title":"LowK wafer dicing robustness considerations and laser grooving process selection","authors":"Patrick Laurent, O. Robin, B. Bouillard","doi":"10.1109/ESTC48849.2020.9229792","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229792","url":null,"abstract":"Zero defect in semiconductor packaging is key especially for high demanding reliability applications (automotive, spatial…) combined with high performance technologies (Silicon ultra lowK wafers 40nm and beyond). The most complex challenge is the Chip Package Interconnect which requires an optimized and controlled singulation process to prevent weaknesses occurring during the process (ILD crack/ delamination, side wall crack, metal burrs, humidity propagation and die strength weakness). Laser grooving prior mechanical dicing offers a good seal ring protection of the chips, ie use of a laser to perform ablation and remove the sawing street contents (dielectric / metallization / patterns) in order to make a clean ‘path’ for the mechanical sawing step afterward. Degradation of the blade condition is also reduced with this approach. This article describes the interactions between laser grooving process and the lLD BEOL delamination prevention by applying a perfect U shape profile.Laser Grooving process selection is a complex combination of different requirements: (i) U shape profile geometry tradeoff to guarantee integrity of BEOL layers during mechanical dicing, while keeping a high level of miniaturization of the sawing street not to increase wafer cost. (ii) Laser technology and process to match the required U-shape geometry minimizing redeposition of residues (recast), avoid pitting (voids) and absorb the heterogenous content of a scribe line with a minimum level of energy applied. This is achieved thanks to an accurate selection of the laser source (wavelength, beam size), accuracy of the beam position (lens optical system), ablation method (multi pass) and process parameter optimization (power, speed, frequency…). (iii) Advanced characterization technics are required to ensure the required quality criteria are matched, like 3D profilometer, FIB cross sections, SEM controls, AOI and 3 points die strength.STMicroelectronics is deploying this quality driven mindset to high volume manufacturing environment in all BE manufacturing plants. Emerging technologies like ultrafast laser wavelength or replacement of mechanical dicing by plasma dicing are next steps of interest further enhanced the robustness of more and more fragile wafer FE technologies.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"162 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75938059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"1700 V full-SiC half-bridge power module with low switching loss","authors":"D. Jung, Hyun Gyu Jang, Doohyung Cho, Kunsik Park, Jong-Won Lim, Joung-Hwan Bae, Yun Hwa Choi","doi":"10.1109/ESTC48849.2020.9229874","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229874","url":null,"abstract":"A 1700 V/200 A half-bridge power module with silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes (SBDs) was researched and developed. Two direct bonded copper (DBC) substrates are interconnected by copper-based clips with width of 6 mm and thickness of 0.8 mm. The DBC substrate and terminals are interconnected by lead free solder alloy. Static and switching characteristics of the power module were tested. The measured turn-on and turn-off switching energies were 20.15 mJ and 3.98 mJ, respectively. We designed and implemented the evaluation circuit board to measure and extract the stray inductance of the module. The extracted stray inductance of the power module was 13.4 nH. Three reliability tests such as high-temperature storage life (HTSL) of 150°C, temperature humidity bias (THB) of 85°C / 85% RH and thermal cycling (TC) of −65~150°C were evaluated. After the reliability tests, the rate of changes of forward current at the same condition was less than 11.98%.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"14 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75617550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ESTC 2020 Ad Page","authors":"","doi":"10.1109/estc48849.2020.9229759","DOIUrl":"https://doi.org/10.1109/estc48849.2020.9229759","url":null,"abstract":"","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"120 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74654241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study of Temperature and Time Dependent Performance Alteration of Silver Ion-exchanged Waveguides in Glass","authors":"L. Brusberg, M. Dejneka, Chad C. Terwilliger, Katerina Rousseva","doi":"10.1109/ESTC48849.2020.9229793","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229793","url":null,"abstract":"Single-mode glass waveguides for a wavelength of 1310 nm were designed in two different glasses with single-mode optical fiber coupling loss of 0.3 dB per interface. The temperature dependent diffusivity of both glasses is studied to explore the thermal alteration of the refractive index profile which can lead to less mode confinement and an increase in optical fiber coupling loss over time. For the model, diffusivity data is collected at higher temperature and extrapolated down to operation temperature range with a peak temperature of 110ºC. The data is verified with experimental data from long term experiments. We study the refractive index change of both glasses and the impact on optical performance over time. One of the selected glasses has almost no alteration and is meeting the data center lifetime requirements of five years. Waveguides were fabricated in both glasses and the lowest propagation loss was measured to be 0.048 dB/cm at a wavelength of 1310 nm.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"61 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83845042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Manufacturing of high frequency substrates as software programmable metasurfaces on PCBs with integrated controller nodes","authors":"D. Manessis, M. Seckel, L. Fu, O. Tsilipakos, A. Pitilakis, A. Tasolamprou, K. Kossifos, G. Varnava, C. Liaskos, M. Kafesaki, C. Soukoulis, S. Tretyakov, Julius Georgiou, A. Ostmann, R. Aschenbrenner, M. Schneider-Ramelow, K. Lang","doi":"10.1109/ESTC48849.2020.9229660","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229660","url":null,"abstract":"The proposed work is performed in the framework of the FET-EU project \"VISORSURF\", which has undertaken research activities on the emerging concepts of metamaterials that can be software programmable and adapt their properties. In the realm of electromagnetism (EM), the field of metasurfaces (MSF) has reached significant breakthroughs in correlating the micro- or nano-structure of artificial planar materials to their end properties. MSFs exhibit physical properties not found in nature, such as negative or smaller-than-unity refraction index, allowing for EM cloaking of objects, reflection cancellation from a given surface and EM energy concentration in as-tight-as-possible spaces.The VISORSURF main objective is the development of a hardware platform, the Hypersurface, whose electromagnetic behavior can be defined programmatically. The key enablers for this are the metasurfaces whose electromagnetic properties depend on their internal structure. The Hypersurface hardware platform will be a 4-layer build-up of high frequency PCB substrate materials and will merge the metasurfaces with custom electronic controller nodes at the bottom of the PCB hardware platform. These electronic controllers build a nanonetwork which receives external programmatic commands and alters the metasurface structure, yielding a desired electromagnetic behavior for the Hypersurface platform.This paper will elaborate on how large scale PCB technologies are deployed for the economical manufacturing of the 4-layer Hypersurface PCB hardware platform with a size of 9\"x12\", having copper metasurface patches on the top of the board and the electronic controllers as 2mmx2mm WLCSP chips at 400µm pitch assembled at the bottom of the platform. The PCB platform designs have stemmed from EM modeling iterations of the whole stack of high frequency laminates taking into account also the electronic features of the controller nodes. The manufacturing processes for the realization of the selected PCB architectures will be discussed in detail.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"20 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82412726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cu pillar based Advanced Packaging, for large area & fine pitch heterogeneous devices","authors":"Abdenacer Ait Mani, Nohora Caicedo, N. Miloud-Ali, F. Levy, F. Berger, T. Mourier, T. Chaira, Natacha R Aphoz, A. Bedoin, P. Peray, M. Francou, A. Gueugnot, L. Boutafa, D. Henry","doi":"10.1109/ESTC48849.2020.9229685","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229685","url":null,"abstract":"The continuous evolution of electronic devices has increased a serious concern on 2.5D and 3D advanced packaging. Applications in domains such as displays, automotive, defense or space, require large volumes of interconnects to cover large areas in order to achieve better performances for monolithic components. One of the main challenges of large surface interconnects for display applications, is the assembly control with a yield close to 100 % on the entire device surface.This must be guaranteed whatever the components shape, their positive or negative bow and warp or its interconnection pitch. The flip-chip based attachment technology using copper (Cu) pillars with tin solder family capping has become the mainstream process choice for fine pitch configurations. Moreover, the industrial supply chain for such kind of interconnections is today available in the packaging industry, however at much higher pitch than that we develop in Research and development level. With the increase of the die dimensions and the decrease of the pitch and bump diameters (higher resolution demand of the market), the associated number of interconnects per device is also increasing. Therefore, the manufacturing challenges in terms of bump height, Cu pillars field, bow and warp variations for such big dies, and the tin oxide issue management, have become extremely stringent. If the pillars are too short, too tall, have large height distribution, or inhomogeneous solder thickness to match the cumulated warpage of the assembly, we will have to face serious hybridization issues. Indeed, the solder during the reflow process will not wet properly the opposite pads or will flow over the copper pillar sides leading to electrical open or short failures. This finally will lead to a poor hybridization yield.The heterogeneity of the stacked materials used to build the active devices (Top dies with polymers, oxides, metals, semiconductors) highly complicates the control of the components behavior at the hybridization temperatures needed by the lead free solders. The same happens when increasing the interconnection area. Indeed, with high bow due to the internal mechanical stress induced by the heterogeneous nature of the components stack, and its resulting shape (concave or convex, or warped); the connections may be only effective at the borders of the sample. As the die attach pattern density becomes complex, sparse on a part of the surface (typically at the edge) and very dense on the other parts (typically in the center), assembly parameters due to such configuration of the devices becomes a big packaging challenge. In this paper, we present hybridizations with high wettability yield of surfaces around 4 cm2, Cu pillars-based on Silicon substrates with 500000 interconnects and compatible with high quality polymer underfilling without voids. The influence of different bow values, assembly parameters and techniques have also been investigated. A particular focus will be made on the","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"1 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82633971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of High Pressures on Au-Sn Solid Liquid Interdiffusion (SLID) Bonds","authors":"Per Kristian Bolstad, S. L. Kuziora, Hoang-Vu Nguyen, T. Manh, K. Aasmundtveit, L. Hoff","doi":"10.1109/ESTC48849.2020.9229855","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229855","url":null,"abstract":"This paper investigates the influence of high pressure on Au-Sn solid-liquid interdiffusion (SLID) bonds formed by bonding Si substrates to dies of either lead-zirconate titanate (PZT) with high surface roughness or Si with low surface roughness. Bonded samples were exposed to 1000 bar pressure in a silicone oil filled pressure vessel. Samples were characterized before and after exposure by means of scanning acoustic microscopy, optical microscopy and scanning electron microscopy with energy dispersive x-ray spectroscopy. All but one sample successfully passed the pressure exposure. This failed sample had a delamination in the proximity of a large void in the intermetallic layer.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"122 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89873813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of a high-speed interconnect","authors":"Christian Johansson","doi":"10.1109/ESTC48849.2020.9229725","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229725","url":null,"abstract":"The use of high-speed applications put a high demand on the interconnects. Methods to investigate the distortion and crosstalk introduced by the interconnects is therefore crucial. Different techniques are available both at the design and at the verification stage of the printed circuit board. In order to determine the quality of a high-speed channel for different operating conditions the S-parameters could be utilized and processed in order to evaluate the performance. This paper presents an overview of a high-speed channel analyzed through the S-parameters utilizing a commercial tool. The performance of the channel and the different techniques are described.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"23 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88726223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Power Conversion Module using LTCC substrate Interconnected to Power Inductor with Low DCR","authors":"H. Jang, D. Jung, Doohyung Cho, Kunsik Park, Jong-Won Lim, Y. Lee","doi":"10.1109/ESTC48849.2020.9229808","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229808","url":null,"abstract":"In this paper, a power inductor embedded pattern with multi-via is proposed to achieve the lower DCR. Also, the low temperature co-fired ceramic (LTCC) substrate for the power conversion module was fabricated to be interconnected with a proposed power inductor. A proposed power inductor can be interconnected to the bottom side of the LTCC substrate. Two types of power inductors were fabricated to compare electrical properties. One is with the single-stack multi-via pattern (SMP) and the other is with the dual-stack multi-via pattern (DMP). The DCR, inductance at the frequency of 1 MHz, and Q-factor at the frequency of 1 MHz for the fabricated inductor with SMP were 17.82 mΩ, 3.21 μH and 42.19, respectively. On the other hand, that of the fabricated inductor with DMP were 12.49 mΩ, 3.3 μH, and 56.77, respectively. Compared to the fabricated inductor with SMP, the inductor with DMP shows lower DCR and higher Q-factor while having a similar inductance. A LTCC based DC-DC converter as the power conversion module was designed to be interconnected with proposed inductors. A DC-DC converter with switching frequency of 1 MHz has input voltage of 12 V, output voltage of 5 V, and rated power of 35 W. The efficiency of the converter with SMP inductor at 35 W was 92.41 % and that of the converter with DMP inductor was 93.79 %. A proposed inductor was designed to minimize DCR and to improve the stability of fabrication. Based on the measured results, it is demonstrated that the DCR is decreased by a proposed structure. This is due to the multi-via pattern in the proposed inductor. It is also proved that a proposed inductor is very suitable for improving the efficiency of the power conversion module.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"141 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89027506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Inline failure analysis of electronic components by infrared thermography without high-emissivity spray coatings","authors":"D. Wargulski, D. May, E. Boschman, A. Hutzler, B. Wunderle, M. A. Ras","doi":"10.1109/ESTC48849.2020.9229787","DOIUrl":"https://doi.org/10.1109/ESTC48849.2020.9229787","url":null,"abstract":"This study shows a technique to avoid the necessary spray-coating of devices under test with low- emissivity surfaces in failure analyses by pulsed IR thermography. Such samples can be sintered or soldered electronic components. The mentioned technique is based on a vacuum foil lamination process, which does not contaminate the samples and saves the time of sample preparations. For this purpose, a suitable and optimal foil must be found, which was the goal of this study. This enables inline inspections in industrial production lines by non-destructive IR thermography methods and an additional alternative to conventional techniques such as scanning acoustic microscopy and x-ray analyses.","PeriodicalId":6785,"journal":{"name":"2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83554177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}